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Add support for the MSI MS-6156 board. 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2009-10-13 19:21:44 +00:00
parent 6bbe74c639
commit 95aa53a5c3
11 changed files with 606 additions and 0 deletions
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1
src/mainboard/msi/Kconfig
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source "src/mainboard/msi/ms6119/Kconfig"
source "src/mainboard/msi/ms6147/Kconfig"
source "src/mainboard/msi/ms6156/Kconfig"
source "src/mainboard/msi/ms6178/Kconfig"
source "src/mainboard/msi/ms7135/Kconfig"
source "src/mainboard/msi/ms7260/Kconfig"

135
src/mainboard/msi/ms6156/Config.lb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 128 * 1024
include /config/nofailovercalculation.lb
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
arch i386 end
driver mainboard.o
if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
makerule ./failover.E
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
dir /pc80
config chip.h
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
device apic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge
device pci 7.0 on # ISA bridge
chip superio/winbond/w83977tf # Super I/O
device pnp 3f0.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 3f0.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 3f0.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 3f0.3 on # COM2 / IR
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 3f0.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # PS/2 keyboard interrupt
irq 0x72 = 12 # PS/2 mouse interrupt
end
device pnp 3f0.7 off # GPIO 1
end
device pnp 3f0.8 off # GPIO 2
end
device pnp 3f0.9 off # GPIO 3
end
device pnp 3f0.a off # ACPI
end
end
end
device pci 7.1 on end # IDE
device pci 7.2 on end # USB
device pci 7.3 on end # ACPI
device pci 14.0 on end # Onboard audio (Ensoniq ES1371)
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "ide_legacy_enable" = "1"
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
register "ide0_drive0_udma33_enable" = "1"
register "ide0_drive1_udma33_enable" = "1"
register "ide1_drive0_udma33_enable" = "1"
register "ide1_drive1_udma33_enable" = "1"
end
end
end

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src/mainboard/msi/ms6156/Kconfig Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config BOARD_MSI_MS_6156
bool "MS-6156"
select ARCH_X86
select CPU_INTEL_SLOT_2
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
config MAINBOARD_DIR
string
default msi/ms6156
depends on BOARD_MSI_MS_6156
config MAINBOARD_PART_NUMBER
string
default "MS-6156"
depends on BOARD_MSI_MS_6156
config HAVE_OPTION_TABLE
bool
default n
depends on BOARD_MSI_MS_6156
config IRQ_SLOT_COUNT
int
default 7
depends on BOARD_MSI_MS_6156

22
src/mainboard/msi/ms6156/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
include $(src)/mainboard/Makefile.romccboard.inc

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src/mainboard/msi/ms6156/Options.lb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_HAVE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses CONFIG_ARCH
uses CONFIG_FALLBACK_SIZE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_ROMBASE
uses CONFIG_RAMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
default CONFIG_ROM_SIZE = 256 * 1024
default CONFIG_HAVE_FALLBACK_BOOT = 1
default CONFIG_HAVE_MP_TABLE = 0
default CONFIG_HAVE_HARD_RESET = 0
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default CONFIG_HAVE_PIRQ_TABLE = 1
default CONFIG_IRQ_SLOT_COUNT = 7
default CONFIG_MAINBOARD_VENDOR = "MSI"
default CONFIG_MAINBOARD_PART_NUMBER = "MS-6156"
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
default CONFIG_STACK_SIZE = 8 * 1024
default CONFIG_HEAP_SIZE = 16 * 1024
default CONFIG_HAVE_OPTION_TABLE = 0
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_USE_OPTION_TABLE = 0
default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CONFIG_CROSS_COMPILE = ""
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_TTYS0_BAUD = 115200
default CONFIG_TTYS0_BASE = 0x3f8
default CONFIG_TTYS0_LCS = 0x3 # 8n1
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1
end

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src/mainboard/msi/ms6156/auto.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
static void main(unsigned long bist)
{
if (bist == 0)
early_mtrr_init();
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
/* ram_check(0, 640 * 1024); */
}

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src/mainboard/msi/ms6156/chip.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations mainboard_ops;
struct mainboard_config {};

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src/mainboard/msi/ms6156/devicetree.cb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
chip northbridge/intel/i440bx # Northbridge
device apic_cluster 0 on # APIC cluster
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
device apic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge
device pci 7.0 on # ISA bridge
chip superio/winbond/w83977tf # Super I/O
device pnp 3f0.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 3f0.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 3f0.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 3f0.3 on # COM2 / IR
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 3f0.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # PS/2 keyboard interrupt
irq 0x72 = 12 # PS/2 mouse interrupt
end
device pnp 3f0.7 off # GPIO 1
end
device pnp 3f0.8 off # GPIO 2
end
device pnp 3f0.9 off # GPIO 3
end
device pnp 3f0.a off # ACPI
end
end
end
device pci 7.1 on end # IDE
device pci 7.2 on end # USB
device pci 7.3 on end # ACPI
device pci 14.0 on end # Onboard audio (Ensoniq ES1371)
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "ide_legacy_enable" = "1"
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
register "ide0_drive0_udma33_enable" = "1"
register "ide0_drive1_udma33_enable" = "1"
register "ide1_drive0_udma33_enable" = "1"
register "ide1_drive1_udma33_enable" = "1"
end
end
end

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src/mainboard/msi/ms6156/irq_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x07 << 3) | 0x0, /* Interrupt router dev */
0x800, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x7000, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xb3, /* Checksum */
{
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x0e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0},
{0x00, (0x10 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0},
{0x00, (0x12 << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0x0},
{0x00, (0x14 << 3) | 0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x4, 0x0},
{0x00, (0x00 << 3) | 0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0},
{0x00, (0x07 << 3) | 0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}

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src/mainboard/msi/ms6156/mainboard.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS-6156 Mainboard")
};

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targets/msi/ms6156/Config.lb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
target ms6156
mainboard msi/ms6156
option CONFIG_ROM_SIZE = 256 * 1024
option CONFIG_MAINBOARD_VENDOR = "MSI"
option CONFIG_MAINBOARD_PART_NUMBER = "MS-6156"
option CONFIG_IRQ_SLOT_COUNT = 7
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
option CONFIG_CONSOLE_VGA = 1
option CONFIG_PCI_ROM_RUN = 1
romimage "normal"
option CONFIG_USE_FALLBACK_IMAGE = 0
option COREBOOT_EXTRA_VERSION = ".0Normal"
payload /tmp/filo.elf
end
romimage "fallback"
option CONFIG_USE_FALLBACK_IMAGE = 1
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload /tmp/filo.elf
end
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"