Add the SuperMicro H8QGI platform
This set adds support for the SuperMicro H8QGI mainboard. It is a publicly available 4 socket board using AMD Family 10 cpus and AMD SR5650 and SB700 bridges. Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/108 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
efdesign98
Marc Jones
parent
3cab93ce8e
commit
95b6611c18
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@ -13,6 +13,8 @@ config BOARD_SUPERMICRO_H8QME_FAM10
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bool "H8QME-2+ (Fam10)"
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bool "H8QME-2+ (Fam10)"
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config BOARD_SUPERMICRO_H8SCM_FAM10
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config BOARD_SUPERMICRO_H8SCM_FAM10
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bool "H8SCM (Fam10)"
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bool "H8SCM (Fam10)"
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config BOARD_SUPERMICRO_H8QGI
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bool "H8QGI"
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config BOARD_SUPERMICRO_X6DAI_G
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config BOARD_SUPERMICRO_X6DAI_G
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bool "X6DAi-G"
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bool "X6DAi-G"
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config BOARD_SUPERMICRO_X6DHE_G2
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config BOARD_SUPERMICRO_X6DHE_G2
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@ -31,6 +33,7 @@ source "src/mainboard/supermicro/h8dmr/Kconfig"
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source "src/mainboard/supermicro/h8dmr_fam10/Kconfig"
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source "src/mainboard/supermicro/h8dmr_fam10/Kconfig"
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source "src/mainboard/supermicro/h8qme_fam10/Kconfig"
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source "src/mainboard/supermicro/h8qme_fam10/Kconfig"
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source "src/mainboard/supermicro/h8scm_fam10/Kconfig"
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source "src/mainboard/supermicro/h8scm_fam10/Kconfig"
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source "src/mainboard/supermicro/h8qgi/Kconfig"
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source "src/mainboard/supermicro/x6dai_g/Kconfig"
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source "src/mainboard/supermicro/x6dai_g/Kconfig"
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source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
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source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
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source "src/mainboard/supermicro/x6dhe_g/Kconfig"
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source "src/mainboard/supermicro/x6dhe_g/Kconfig"
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@ -0,0 +1,516 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "agesawrapper.h"
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#include "amdlib.h"
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#include "BiosCallOuts.h"
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#include "Ids.h"
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#include "OptionsIds.h"
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#include "heapManager.h"
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STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
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{
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{
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AGESA_ALLOCATE_BUFFER,
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BiosAllocateBuffer
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},
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{
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AGESA_DEALLOCATE_BUFFER,
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BiosDeallocateBuffer
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},
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{
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AGESA_DO_RESET,
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BiosReset
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},
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{
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AGESA_LOCATE_BUFFER,
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BiosLocateBuffer
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},
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{
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AGESA_READ_SPD,
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BiosReadSpd
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},
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{
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AGESA_READ_SPD_RECOVERY,
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BiosDefaultRet
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},
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{
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AGESA_RUNFUNC_ONAP,
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BiosRunFuncOnAp
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},
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{
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AGESA_GET_IDS_INIT_DATA,
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BiosGetIdsInitData
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},
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{
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AGESA_HOOKBEFORE_DQS_TRAINING,
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BiosHookBeforeDQSTraining
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},
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{
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AGESA_HOOKBEFORE_DRAM_INIT,
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BiosHookBeforeDramInit
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},
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{
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AGESA_HOOKBEFORE_EXIT_SELF_REF,
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BiosHookBeforeExitSelfRefresh
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},
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};
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extern AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
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AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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UINTN i;
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AGESA_STATUS CalloutStatus;
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for (i = 0; i < REQUIRED_CALLOUTS; i++) {
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if (BiosCallouts[i].CalloutName == Func) {
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break;
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}
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}
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if(i >= REQUIRED_CALLOUTS) {
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return AGESA_UNSUPPORTED;
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}
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CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
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return CalloutStatus;
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}
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CONST IDS_NV_ITEM IdsData[] =
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{
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/*{
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AGESA_IDS_NV_MAIN_PLL_CON,
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0x1
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},
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{
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AGESA_IDS_NV_MAIN_PLL_FID_EN,
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0x1
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},
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{
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AGESA_IDS_NV_MAIN_PLL_FID,
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0x8
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},
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{
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AGESA_IDS_NV_CUSTOM_NB_PSTATE,
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},
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{
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AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
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},
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{
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AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
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},
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{
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AGESA_IDS_NV_FORCE_NB_PSTATE,
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},
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*/
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{
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0xFFFF,
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0xFFFF
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}
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};
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#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
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AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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UINTN i;
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IDS_NV_ITEM *IdsPtr;
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IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
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if (Data == IDS_CALLOUT_INIT) {
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for (i = 0; i < NUM_IDS_ENTRIES; i++) {
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IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
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IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
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}
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}
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return AGESA_SUCCESS;
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}
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AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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UINT32 AvailableHeapSize;
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UINT8 *BiosHeapBaseAddr;
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UINT32 CurrNodeOffset;
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UINT32 PrevNodeOffset;
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UINT32 FreedNodeOffset;
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UINT32 BestFitNodeOffset;
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UINT32 BestFitPrevNodeOffset;
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UINT32 NextFreeOffset;
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BIOS_BUFFER_NODE *CurrNodePtr;
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BIOS_BUFFER_NODE *FreedNodePtr;
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BIOS_BUFFER_NODE *BestFitNodePtr;
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BIOS_BUFFER_NODE *BestFitPrevNodePtr;
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BIOS_BUFFER_NODE *NextFreePtr;
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BIOS_HEAP_MANAGER *BiosHeapBasePtr;
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AGESA_BUFFER_PARAMS *AllocParams;
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AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
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AllocParams->BufferPointer = NULL;
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AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
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BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
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BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
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if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
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/* First allocation */
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CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
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CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
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CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
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CurrNodePtr->BufferSize = AllocParams->BufferLength;
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CurrNodePtr->NextNodeOffset = 0;
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AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
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/* Update the remaining free space */
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FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
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FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
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FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
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FreedNodePtr->NextNodeOffset = 0;
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/* Update the offsets for Allocated and Freed nodes */
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BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
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BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
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} else {
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/* Find out whether BufferHandle has been allocated on the heap. */
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/* If it has, return AGESA_BOUNDS_CHK */
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CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
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CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
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while (CurrNodeOffset != 0) {
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CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
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if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
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return AGESA_BOUNDS_CHK;
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}
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CurrNodeOffset = CurrNodePtr->NextNodeOffset;
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/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
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to the end of the allocated nodes list.
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*/
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}
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/* Find the node that best fits the requested buffer size */
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FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
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PrevNodeOffset = FreedNodeOffset;
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BestFitNodeOffset = 0;
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BestFitPrevNodeOffset = 0;
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while (FreedNodeOffset != 0) {
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FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
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if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
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if (BestFitNodeOffset == 0) {
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/* First node that fits the requested buffer size */
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BestFitNodeOffset = FreedNodeOffset;
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BestFitPrevNodeOffset = PrevNodeOffset;
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} else {
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/* Find out whether current node is a better fit than the previous nodes */
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BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
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if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
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BestFitNodeOffset = FreedNodeOffset;
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BestFitPrevNodeOffset = PrevNodeOffset;
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}
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}
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}
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PrevNodeOffset = FreedNodeOffset;
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FreedNodeOffset = FreedNodePtr->NextNodeOffset;
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} /* end of while loop */
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if (BestFitNodeOffset == 0) {
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/* If we could not find a node that fits the requested buffer */
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/* size, return AGESA_BOUNDS_CHK */
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return AGESA_BOUNDS_CHK;
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} else {
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BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
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BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
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/* If BestFitNode is larger than the requested buffer, fragment the node further */
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if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
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NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
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NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
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NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
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NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
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} else {
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/* Otherwise, next free node is NextNodeOffset of BestFitNode */
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NextFreeOffset = BestFitNodePtr->NextNodeOffset;
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}
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/* If BestFitNode is the first buffer in the list, then update
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StartOfFreedNodes to reflect the new free node
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*/
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if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
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BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
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} else {
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BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
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}
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/* Add BestFitNode to the list of Allocated nodes */
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CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
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BestFitNodePtr->BufferSize = AllocParams->BufferLength;
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BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
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BestFitNodePtr->NextNodeOffset = 0;
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/* Remove BestFitNode from list of Freed nodes */
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AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
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}
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}
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return AGESA_SUCCESS;
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}
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AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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UINT8 *BiosHeapBaseAddr;
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UINT32 AllocNodeOffset;
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UINT32 PrevNodeOffset;
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UINT32 NextNodeOffset;
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UINT32 FreedNodeOffset;
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UINT32 EndNodeOffset;
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BIOS_BUFFER_NODE *AllocNodePtr;
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BIOS_BUFFER_NODE *PrevNodePtr;
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BIOS_BUFFER_NODE *FreedNodePtr;
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BIOS_BUFFER_NODE *NextNodePtr;
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BIOS_HEAP_MANAGER *BiosHeapBasePtr;
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AGESA_BUFFER_PARAMS *AllocParams;
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BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
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BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
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AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
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/* Find target node to deallocate in list of allocated nodes.
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Return AGESA_BOUNDS_CHK if the BufferHandle is not found
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*/
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AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
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AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
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PrevNodeOffset = AllocNodeOffset;
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while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
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if (AllocNodePtr->NextNodeOffset == 0) {
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return AGESA_BOUNDS_CHK;
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}
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PrevNodeOffset = AllocNodeOffset;
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AllocNodeOffset = AllocNodePtr->NextNodeOffset;
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AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
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}
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/* Remove target node from list of allocated nodes */
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PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
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PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
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/* Zero out the buffer, and clear the BufferHandle */
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LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
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AllocNodePtr->BufferHandle = 0;
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AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
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|
||||||
|
/* Add deallocated node in order to the list of freed nodes */
|
||||||
|
FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
|
||||||
|
FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
|
||||||
|
|
||||||
|
EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
|
||||||
|
|
||||||
|
if (AllocNodeOffset < FreedNodeOffset) {
|
||||||
|
/* Add to the start of the freed list */
|
||||||
|
if (EndNodeOffset == FreedNodeOffset) {
|
||||||
|
/* If the freed node is adjacent to the first node in the list, concatenate both nodes */
|
||||||
|
AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
|
||||||
|
AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
|
||||||
|
|
||||||
|
/* Clear the BufferSize and NextNodeOffset of the previous first node */
|
||||||
|
FreedNodePtr->BufferSize = 0;
|
||||||
|
FreedNodePtr->NextNodeOffset = 0;
|
||||||
|
|
||||||
|
} else {
|
||||||
|
/* Otherwise, add freed node to the start of the list
|
||||||
|
Update NextNodeOffset and BufferSize to include the
|
||||||
|
size of BIOS_BUFFER_NODE
|
||||||
|
*/
|
||||||
|
AllocNodePtr->NextNodeOffset = FreedNodeOffset;
|
||||||
|
}
|
||||||
|
/* Update StartOfFreedNodes to the new first node */
|
||||||
|
BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
|
||||||
|
} else {
|
||||||
|
/* Traverse list of freed nodes to find where the deallocated node
|
||||||
|
should be place
|
||||||
|
*/
|
||||||
|
NextNodeOffset = FreedNodeOffset;
|
||||||
|
NextNodePtr = FreedNodePtr;
|
||||||
|
while (AllocNodeOffset > NextNodeOffset) {
|
||||||
|
PrevNodeOffset = NextNodeOffset;
|
||||||
|
if (NextNodePtr->NextNodeOffset == 0) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
NextNodeOffset = NextNodePtr->NextNodeOffset;
|
||||||
|
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* If deallocated node is adjacent to the next node,
|
||||||
|
concatenate both nodes
|
||||||
|
*/
|
||||||
|
if (NextNodeOffset == EndNodeOffset) {
|
||||||
|
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
|
||||||
|
AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
|
||||||
|
AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
|
||||||
|
|
||||||
|
NextNodePtr->BufferSize = 0;
|
||||||
|
NextNodePtr->NextNodeOffset = 0;
|
||||||
|
} else {
|
||||||
|
/*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
|
||||||
|
AllocNodePtr->NextNodeOffset = NextNodeOffset;
|
||||||
|
}
|
||||||
|
/* If deallocated node is adjacent to the previous node,
|
||||||
|
concatenate both nodes
|
||||||
|
*/
|
||||||
|
PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
|
||||||
|
EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
|
||||||
|
if (AllocNodeOffset == EndNodeOffset) {
|
||||||
|
PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
|
||||||
|
PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
|
||||||
|
|
||||||
|
AllocNodePtr->BufferSize = 0;
|
||||||
|
AllocNodePtr->NextNodeOffset = 0;
|
||||||
|
} else {
|
||||||
|
PrevNodePtr->NextNodeOffset = AllocNodeOffset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return AGESA_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
|
||||||
|
{
|
||||||
|
UINT32 AllocNodeOffset;
|
||||||
|
UINT8 *BiosHeapBaseAddr;
|
||||||
|
BIOS_BUFFER_NODE *AllocNodePtr;
|
||||||
|
BIOS_HEAP_MANAGER *BiosHeapBasePtr;
|
||||||
|
AGESA_BUFFER_PARAMS *AllocParams;
|
||||||
|
|
||||||
|
AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
|
||||||
|
|
||||||
|
BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
|
||||||
|
BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
|
||||||
|
|
||||||
|
AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
|
||||||
|
AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
|
||||||
|
|
||||||
|
while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
|
||||||
|
if (AllocNodePtr->NextNodeOffset == 0) {
|
||||||
|
AllocParams->BufferPointer = NULL;
|
||||||
|
AllocParams->BufferLength = 0;
|
||||||
|
return AGESA_BOUNDS_CHK;
|
||||||
|
} else {
|
||||||
|
AllocNodeOffset = AllocNodePtr->NextNodeOffset;
|
||||||
|
AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
|
||||||
|
AllocParams->BufferLength = AllocNodePtr->BufferSize;
|
||||||
|
|
||||||
|
return AGESA_SUCCESS;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
|
||||||
|
{
|
||||||
|
AGESA_STATUS Status;
|
||||||
|
|
||||||
|
Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
|
||||||
|
return Status;
|
||||||
|
}
|
||||||
|
|
||||||
|
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
|
||||||
|
{
|
||||||
|
AGESA_STATUS Status;
|
||||||
|
UINT8 Value;
|
||||||
|
UINTN ResetType;
|
||||||
|
AMD_CONFIG_PARAMS *StdHeader;
|
||||||
|
|
||||||
|
ResetType = Data;
|
||||||
|
StdHeader = ConfigPtr;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Perform the RESET based upon the ResetType. In case of
|
||||||
|
// WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
|
||||||
|
// AmdResetManager. During the critical condition, where reset is required
|
||||||
|
// immediately, the reset will be invoked directly by writing 0x04 to port
|
||||||
|
// 0xCF9 (Reset Port).
|
||||||
|
//
|
||||||
|
switch (ResetType) {
|
||||||
|
case WARM_RESET_WHENEVER:
|
||||||
|
case COLD_RESET_WHENEVER:
|
||||||
|
break;
|
||||||
|
|
||||||
|
case WARM_RESET_IMMEDIATELY:
|
||||||
|
case COLD_RESET_IMMEDIATELY:
|
||||||
|
Value = 0x06;
|
||||||
|
LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
Status = 0;
|
||||||
|
return Status;
|
||||||
|
}
|
||||||
|
|
||||||
|
AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
|
||||||
|
{
|
||||||
|
AGESA_STATUS Status;
|
||||||
|
Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
|
||||||
|
|
||||||
|
return Status;
|
||||||
|
}
|
||||||
|
|
||||||
|
AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
|
||||||
|
{
|
||||||
|
return AGESA_UNSUPPORTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Call the host environment interface to provide a user hook opportunity. */
|
||||||
|
AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
|
||||||
|
{
|
||||||
|
return AGESA_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Call the host environment interface to provide a user hook opportunity. */
|
||||||
|
AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
|
||||||
|
{
|
||||||
|
return AGESA_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Call the host environment interface to provide a user hook opportunity. */
|
||||||
|
AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
|
||||||
|
{
|
||||||
|
return AGESA_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,78 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _BIOS_CALLOUT_H_
|
||||||
|
#define _BIOS_CALLOUT_H_
|
||||||
|
|
||||||
|
#include "Porting.h"
|
||||||
|
#include "AGESA.h"
|
||||||
|
|
||||||
|
#define REQUIRED_CALLOUTS 12
|
||||||
|
#define BIOS_HEAP_START_ADDRESS 0x00010000
|
||||||
|
#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
|
||||||
|
|
||||||
|
typedef struct _BIOS_HEAP_MANAGER {
|
||||||
|
//UINT32 AvailableSize;
|
||||||
|
UINT32 StartOfAllocatedNodes;
|
||||||
|
UINT32 StartOfFreedNodes;
|
||||||
|
} BIOS_HEAP_MANAGER;
|
||||||
|
|
||||||
|
typedef struct _BIOS_BUFFER_NODE {
|
||||||
|
UINT32 BufferHandle;
|
||||||
|
UINT32 BufferSize;
|
||||||
|
UINT32 NextNodeOffset;
|
||||||
|
} BIOS_BUFFER_NODE;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* CALLOUTS
|
||||||
|
*/
|
||||||
|
AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
|
||||||
|
/* REQUIRED CALLOUTS
|
||||||
|
* AGESA ADVANCED CALLOUTS - CPU
|
||||||
|
*/
|
||||||
|
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
|
||||||
|
/* AGESA ADVANCED CALLOUTS - MEMORY */
|
||||||
|
AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);
|
||||||
|
|
||||||
|
/* BIOS DEFAULT RET */
|
||||||
|
AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
|
||||||
|
/* Call the host environment interface to provide a user hook opportunity. */
|
||||||
|
AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
/* Call the host environment interface to provide a user hook opportunity. */
|
||||||
|
AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
/* Call the host environment interface to provide a user hook opportunity. */
|
||||||
|
AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
|
||||||
|
#define SB_GPIO_REG02 2
|
||||||
|
#define SB_GPIO_REG09 9
|
||||||
|
#define SB_GPIO_REG10 10
|
||||||
|
#define SB_GPIO_REG15 15
|
||||||
|
#define SB_GPIO_REG17 17
|
||||||
|
#define SB_GPIO_REG21 21
|
||||||
|
#define SB_GPIO_REG25 25
|
||||||
|
#define SB_GPIO_REG28 28
|
||||||
|
#endif //_BIOS_CALLOUT_H_
|
||||||
|
|
||||||
|
|
@ -0,0 +1,129 @@
|
||||||
|
#
|
||||||
|
# This file is part of the coreboot project.
|
||||||
|
#
|
||||||
|
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or modify
|
||||||
|
# it under the terms of the GNU General Public License as published by
|
||||||
|
# the Free Software Foundation; version 2 of the License.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
if BOARD_SUPERMICRO_H8QGI
|
||||||
|
|
||||||
|
config BOARD_SPECIFIC_OPTIONS
|
||||||
|
def_bool y
|
||||||
|
select ARCH_X86
|
||||||
|
select CPU_AMD_AGESA_FAMILY10
|
||||||
|
select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX
|
||||||
|
select NORTHBRIDGE_AMD_AGESA_FAMILY10
|
||||||
|
select SOUTHBRIDGE_AMD_SR5650
|
||||||
|
select SOUTHBRIDGE_AMD_SP5100
|
||||||
|
select SUPERIO_WINBOND_W83627DHG
|
||||||
|
select BOARD_HAS_FADT
|
||||||
|
select HAVE_BUS_CONFIG
|
||||||
|
select HAVE_OPTION_TABLE
|
||||||
|
select HAVE_PIRQ_TABLE
|
||||||
|
select HAVE_MP_TABLE
|
||||||
|
select HAVE_HARD_RESET
|
||||||
|
select SERIAL_CPU_INIT
|
||||||
|
select AMDMCT
|
||||||
|
select HAVE_ACPI_TABLES
|
||||||
|
select BOARD_ROMSIZE_KB_2048
|
||||||
|
select TINY_BOOTBLOCK
|
||||||
|
#select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict
|
||||||
|
|
||||||
|
config AMD_AGESA
|
||||||
|
bool
|
||||||
|
default y
|
||||||
|
|
||||||
|
config MAINBOARD_DIR
|
||||||
|
string
|
||||||
|
default supermicro/h8qgi
|
||||||
|
|
||||||
|
config MAINBOARD_PART_NUMBER
|
||||||
|
string
|
||||||
|
default "H8QGI"
|
||||||
|
|
||||||
|
config HW_MEM_HOLE_SIZEK
|
||||||
|
hex
|
||||||
|
default 0x200000
|
||||||
|
|
||||||
|
config MAX_CPUS
|
||||||
|
int
|
||||||
|
default 64
|
||||||
|
|
||||||
|
config MAX_PHYSICAL_CPUS
|
||||||
|
int
|
||||||
|
default 16
|
||||||
|
|
||||||
|
config HW_MEM_HOLE_SIZE_AUTO_INC
|
||||||
|
bool
|
||||||
|
default n
|
||||||
|
|
||||||
|
config MEM_TRAIN_SEQ
|
||||||
|
int
|
||||||
|
default 2
|
||||||
|
|
||||||
|
config IRQ_SLOT_COUNT
|
||||||
|
int
|
||||||
|
default 11
|
||||||
|
|
||||||
|
config RAMTOP
|
||||||
|
hex
|
||||||
|
default 0x1000000
|
||||||
|
|
||||||
|
config HEAP_SIZE
|
||||||
|
hex
|
||||||
|
default 0xc0000
|
||||||
|
|
||||||
|
config STACK_SIZE
|
||||||
|
hex
|
||||||
|
default 0x10000
|
||||||
|
|
||||||
|
config ACPI_SSDTX_NUM
|
||||||
|
int
|
||||||
|
default 0
|
||||||
|
|
||||||
|
config RAMBASE
|
||||||
|
hex
|
||||||
|
default 0x200000
|
||||||
|
|
||||||
|
config SIO_PORT
|
||||||
|
hex
|
||||||
|
default 0x164E
|
||||||
|
help
|
||||||
|
though UARTs are on the NUVOTON BMC, port 0x164E
|
||||||
|
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
|
||||||
|
|
||||||
|
config DRIVERS_PS2_KEYBOARD
|
||||||
|
bool
|
||||||
|
default y
|
||||||
|
|
||||||
|
config WARNINGS_ARE_ERRORS
|
||||||
|
bool
|
||||||
|
default n
|
||||||
|
|
||||||
|
config ONBOARD_VGA_IS_PRIMARY
|
||||||
|
bool
|
||||||
|
default y
|
||||||
|
|
||||||
|
config VGA_BIOS
|
||||||
|
bool
|
||||||
|
default n
|
||||||
|
|
||||||
|
config VGA_BIOS_ID
|
||||||
|
string
|
||||||
|
depends on VGA_BIOS
|
||||||
|
default "102b,0532"
|
||||||
|
|
||||||
|
endif # BOARD_SUPERMICRO_H8QGI
|
||||||
|
|
||||||
|
|
@ -0,0 +1,33 @@
|
||||||
|
#
|
||||||
|
# This file is part of the coreboot project.
|
||||||
|
#
|
||||||
|
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or modify
|
||||||
|
# it under the terms of the GNU General Public License as published by
|
||||||
|
# the Free Software Foundation; version 2 of the License.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
romstage-y += buildOpts.c
|
||||||
|
romstage-y += agesawrapper.c
|
||||||
|
romstage-y += dimmSpd.c
|
||||||
|
romstage-y += BiosCallOuts.c
|
||||||
|
romstage-y += platform_oem.c
|
||||||
|
|
||||||
|
ramstage-y += buildOpts.c
|
||||||
|
ramstage-y += agesawrapper.c
|
||||||
|
ramstage-y += dimmSpd.c
|
||||||
|
ramstage-y += BiosCallOuts.c
|
||||||
|
ramstage-y += platform_oem.c
|
||||||
|
|
||||||
|
AGESA_ROOT ?= $(src)/vendorcode/amd/agesa/f10/
|
||||||
|
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += ../../../../$(AGESA_ROOT)
|
||||||
|
|
@ -0,0 +1,66 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file
|
||||||
|
*
|
||||||
|
* IDS Option File
|
||||||
|
*
|
||||||
|
* This file is used to switch on/off IDS features.
|
||||||
|
*
|
||||||
|
* @xrefitem bom "File Content Label" "Release Content"
|
||||||
|
* @e project: AGESA
|
||||||
|
* @e sub-project: Core
|
||||||
|
* @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
|
||||||
|
*/
|
||||||
|
#ifndef _OPTION_IDS_H_
|
||||||
|
#define _OPTION_IDS_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
*
|
||||||
|
* This file generates the defaults tables for the Integrated Debug Support
|
||||||
|
* Module. The documented build options are imported from a user controlled
|
||||||
|
* file for processing. The build options for the Integrated Debug Support
|
||||||
|
* Module are listed below:
|
||||||
|
*
|
||||||
|
* IDSOPT_IDS_ENABLED
|
||||||
|
* IDSOPT_ERROR_TRAP_ENABLED
|
||||||
|
* IDSOPT_CONTROL_ENABLED
|
||||||
|
* IDSOPT_TRACING_ENABLED
|
||||||
|
* IDSOPT_PERF_ANALYSIS
|
||||||
|
* IDSOPT_ASSERT_ENABLED
|
||||||
|
* IDS_DEBUG_PORT
|
||||||
|
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
|
||||||
|
*
|
||||||
|
**/
|
||||||
|
|
||||||
|
#define IDSOPT_IDS_ENABLED TRUE
|
||||||
|
//#define IDSOPT_CONTROL_ENABLED TRUE
|
||||||
|
#define IDSOPT_TRACING_ENABLED TRUE
|
||||||
|
//#define IDSOPT_PERF_ANALYSIS TRUE
|
||||||
|
#define IDSOPT_ASSERT_ENABLED TRUE
|
||||||
|
//#undef IDSOPT_DEBUG_ENABLED
|
||||||
|
//#define IDSOPT_DEBUG_ENABLED FALSE
|
||||||
|
//#undef IDSOPT_HOST_SIMNOW
|
||||||
|
//#define IDSOPT_HOST_SIMNOW FALSE
|
||||||
|
//#undef IDSOPT_HOST_HDT
|
||||||
|
//#define IDSOPT_HOST_HDT FALSE
|
||||||
|
//#define IDS_DEBUG_PORT 0x80
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,75 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* This file defines the processor and performance state capability
|
||||||
|
* for each core in the system. It is included into the DSDT for each
|
||||||
|
* core. It assumes that each core of the system has the same performance
|
||||||
|
* characteristics.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
|
||||||
|
{
|
||||||
|
Scope (\_PR) {
|
||||||
|
Processor(CPU0,0,0x808,0x06) {
|
||||||
|
#include "cpstate.asl"
|
||||||
|
}
|
||||||
|
Processor(CPU1,1,0x0,0x0) {
|
||||||
|
#include "cpstate.asl"
|
||||||
|
}
|
||||||
|
Processor(CPU2,2,0x0,0x0) {
|
||||||
|
#include "cpstate.asl"
|
||||||
|
}
|
||||||
|
Processor(CPU3,3,0x0,0x0) {
|
||||||
|
#include "cpstate.asl"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
/* P-state support: The maximum number of P-states supported by the */
|
||||||
|
/* CPUs we'll use is 6. */
|
||||||
|
/* Get from AMI BIOS. */
|
||||||
|
Name(_PSS, Package(){
|
||||||
|
Package ()
|
||||||
|
{
|
||||||
|
0x00000AF0,
|
||||||
|
0x0000BF81,
|
||||||
|
0x00000002,
|
||||||
|
0x00000002,
|
||||||
|
0x00000000,
|
||||||
|
0x00000000
|
||||||
|
},
|
||||||
|
|
||||||
|
Package ()
|
||||||
|
{
|
||||||
|
0x00000578,
|
||||||
|
0x000076F2,
|
||||||
|
0x00000002,
|
||||||
|
0x00000002,
|
||||||
|
0x00000001,
|
||||||
|
0x00000001
|
||||||
|
}
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(_PCT, Package(){
|
||||||
|
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
|
||||||
|
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
|
||||||
|
})
|
||||||
|
|
||||||
|
Method(_PPC, 0){
|
||||||
|
Return(0)
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,244 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Scope (_SB) {
|
||||||
|
Device(PCI0) {
|
||||||
|
Device(IDEC) {
|
||||||
|
Name(_ADR, 0x00140001)
|
||||||
|
#include "ide.asl"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Some timing tables */
|
||||||
|
Name(UDTT, Package(){ /* Udma timing table */
|
||||||
|
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(MDTT, Package(){ /* MWDma timing table */
|
||||||
|
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(POTT, Package(){ /* Pio timing table */
|
||||||
|
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
|
||||||
|
})
|
||||||
|
|
||||||
|
/* Some timing register value tables */
|
||||||
|
Name(MDRT, Package(){ /* MWDma timing register table */
|
||||||
|
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(PORT, Package(){
|
||||||
|
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
|
||||||
|
})
|
||||||
|
|
||||||
|
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
|
||||||
|
Field(ICRG, AnyAcc, NoLock, Preserve)
|
||||||
|
{
|
||||||
|
PPTS, 8, /* Primary PIO Slave Timing */
|
||||||
|
PPTM, 8, /* Primary PIO Master Timing */
|
||||||
|
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
|
||||||
|
PMTM, 8, /* Primary MWDMA Master Timing */
|
||||||
|
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
|
||||||
|
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
|
||||||
|
PPSM, 4, /* Primary PIO slave Mode */
|
||||||
|
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
|
||||||
|
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
|
||||||
|
PDSM, 4, /* Primary UltraDMA Mode */
|
||||||
|
}
|
||||||
|
|
||||||
|
Method(GTTM, 1) /* get total time*/
|
||||||
|
{
|
||||||
|
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
|
||||||
|
Increment(Local0)
|
||||||
|
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
|
||||||
|
Increment(Local1)
|
||||||
|
Return(Multiply(30, Add(Local0, Local1)))
|
||||||
|
}
|
||||||
|
|
||||||
|
Device(PRID)
|
||||||
|
{
|
||||||
|
Name (_ADR, Zero)
|
||||||
|
Method(_GTM, 0)
|
||||||
|
{
|
||||||
|
NAME(OTBF, Buffer(20) { /* out buffer */
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||||
|
})
|
||||||
|
|
||||||
|
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
|
||||||
|
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
|
||||||
|
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
|
||||||
|
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
|
||||||
|
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
|
||||||
|
|
||||||
|
/* Just return if the channel is disabled */
|
||||||
|
If(And(PPCR, 0x01)) { /* primary PIO control */
|
||||||
|
Return(OTBF)
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Always tell them independent timing available and IOChannelReady used on both drives */
|
||||||
|
Or(BFFG, 0x1A, BFFG)
|
||||||
|
|
||||||
|
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
|
||||||
|
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
|
||||||
|
|
||||||
|
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
|
||||||
|
Or(BFFG, 0x01, BFFG)
|
||||||
|
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
|
||||||
|
}
|
||||||
|
Else {
|
||||||
|
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
|
||||||
|
}
|
||||||
|
|
||||||
|
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
|
||||||
|
Or(BFFG, 0x04, BFFG)
|
||||||
|
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
|
||||||
|
}
|
||||||
|
Else {
|
||||||
|
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
|
||||||
|
}
|
||||||
|
|
||||||
|
Return(OTBF) /* out buffer */
|
||||||
|
} /* End Method(_GTM) */
|
||||||
|
|
||||||
|
Method(_STM, 3, NotSerialized)
|
||||||
|
{
|
||||||
|
NAME(INBF, Buffer(20) { /* in buffer */
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
|
||||||
|
})
|
||||||
|
|
||||||
|
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
|
||||||
|
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
|
||||||
|
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
|
||||||
|
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
|
||||||
|
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
|
||||||
|
|
||||||
|
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
|
||||||
|
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
|
||||||
|
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
|
||||||
|
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
|
||||||
|
|
||||||
|
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
|
||||||
|
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
|
||||||
|
|
||||||
|
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
|
||||||
|
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||||
|
Divide(Local0, 7, PDMM,)
|
||||||
|
Or(PDCR, 0x01, PDCR)
|
||||||
|
}
|
||||||
|
Else {
|
||||||
|
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
|
||||||
|
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
|
||||||
|
Store(DerefOf(Index(MDRT, Local0)), PMTM)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
|
||||||
|
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||||
|
Divide(Local0, 7, PDSM,)
|
||||||
|
Or(PDCR, 0x02, PDCR)
|
||||||
|
}
|
||||||
|
Else {
|
||||||
|
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
|
||||||
|
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
|
||||||
|
Store(DerefOf(Index(MDRT, Local0)), PMTS)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Return(INBF) */
|
||||||
|
} /*End Method(_STM) */
|
||||||
|
Device(MST)
|
||||||
|
{
|
||||||
|
Name(_ADR, 0)
|
||||||
|
Method(_GTF) {
|
||||||
|
Name(CMBF, Buffer(21) {
|
||||||
|
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||||
|
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||||
|
})
|
||||||
|
CreateByteField(CMBF, 1, POMD)
|
||||||
|
CreateByteField(CMBF, 8, DMMD)
|
||||||
|
CreateByteField(CMBF, 5, CMDA)
|
||||||
|
CreateByteField(CMBF, 12, CMDB)
|
||||||
|
CreateByteField(CMBF, 19, CMDC)
|
||||||
|
|
||||||
|
Store(0xA0, CMDA)
|
||||||
|
Store(0xA0, CMDB)
|
||||||
|
Store(0xA0, CMDC)
|
||||||
|
|
||||||
|
Or(PPMM, 0x08, POMD)
|
||||||
|
|
||||||
|
If(And(PDCR, 0x01)) {
|
||||||
|
Or(PDMM, 0x40, DMMD)
|
||||||
|
}
|
||||||
|
Else {
|
||||||
|
Store(Match
|
||||||
|
(MDTT, MLE, GTTM(PMTM),
|
||||||
|
MTR, 0, 0), Local0)
|
||||||
|
If(LLess(Local0, 3)) {
|
||||||
|
Or(0x20, Local0, DMMD)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Return(CMBF)
|
||||||
|
}
|
||||||
|
} /* End Device(MST) */
|
||||||
|
|
||||||
|
Device(SLAV)
|
||||||
|
{
|
||||||
|
Name(_ADR, 1)
|
||||||
|
Method(_GTF) {
|
||||||
|
Name(CMBF, Buffer(21) {
|
||||||
|
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||||
|
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
|
||||||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
|
||||||
|
})
|
||||||
|
CreateByteField(CMBF, 1, POMD)
|
||||||
|
CreateByteField(CMBF, 8, DMMD)
|
||||||
|
CreateByteField(CMBF, 5, CMDA)
|
||||||
|
CreateByteField(CMBF, 12, CMDB)
|
||||||
|
CreateByteField(CMBF, 19, CMDC)
|
||||||
|
|
||||||
|
Store(0xB0, CMDA)
|
||||||
|
Store(0xB0, CMDB)
|
||||||
|
Store(0xB0, CMDC)
|
||||||
|
|
||||||
|
Or(PPSM, 0x08, POMD)
|
||||||
|
|
||||||
|
If(And(PDCR, 0x02)) {
|
||||||
|
Or(PDSM, 0x40, DMMD)
|
||||||
|
}
|
||||||
|
Else {
|
||||||
|
Store(Match
|
||||||
|
(MDTT, MLE, GTTM(PMTS),
|
||||||
|
MTR, 0, 0), Local0)
|
||||||
|
If(LLess(Local0, 3)) {
|
||||||
|
Or(0x20, Local0, DMMD)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Return(CMBF)
|
||||||
|
}
|
||||||
|
} /* End Device(SLAV) */
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,222 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||||
|
)
|
||||||
|
{
|
||||||
|
#include "routing.asl"
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Routing is in System Bus scope */
|
||||||
|
Scope(\_SB) {
|
||||||
|
Name(PR0, Package(){
|
||||||
|
/* NB devices */
|
||||||
|
/* Bus 0, Dev 0 - SR5650 HT */
|
||||||
|
Package() { 0xFFFF, Zero, INTA, Zero },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 1 - CLKCONFIG */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
|
||||||
|
Package() {0x0002FFFF, 0, INTE, 0 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||||
|
Package() {0x0004FFFF, 0, INTE, 0 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 9 - PCIe Bridge */
|
||||||
|
|
||||||
|
/* Bus 0, Dev a - PCIe Bridge */
|
||||||
|
|
||||||
|
/* Bus 0, Dev b - PCIe Bridge */
|
||||||
|
Package() {0x000BFFFF, 0, INTG, 0 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev c - PCIe Bridge */
|
||||||
|
Package() {0x000CFFFF, 0, INTG, 0 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/
|
||||||
|
Package() {0x000DFFFF, 0, INTG, 0 },
|
||||||
|
|
||||||
|
/* SB devices */
|
||||||
|
/* Bus 0, Dev 17 - SATA controller */
|
||||||
|
Package() {0x0011FFFF, 0, INTG, 0 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||||
|
* EHCI, dev 18, 19 func 2 */
|
||||||
|
Package() {0x0012FFFF, 0, INTA, 0 },
|
||||||
|
Package() {0x0012FFFF, 1, INTB, 0 },
|
||||||
|
Package() {0x0012FFFF, 2, INTC, 0 },
|
||||||
|
Package() {0x0012FFFF, 3, INTD, 0 },
|
||||||
|
|
||||||
|
Package() {0x0013FFFF, 0, INTC, 0 },
|
||||||
|
Package() {0x0013FFFF, 1, INTD, 0 },
|
||||||
|
Package() {0x0013FFFF, 2, INTA, 0 },
|
||||||
|
Package() {0x0013FFFF, 2, INTB, 0 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
|
||||||
|
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||||
|
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||||
|
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||||
|
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(APR0, Package(){
|
||||||
|
/* NB devices in APIC mode */
|
||||||
|
/* Bus 0, Dev 0 - SR5650 HT */
|
||||||
|
Package() { 0xFFFF, Zero, Zero, 16 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 1 - CLKCONFIG */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */
|
||||||
|
Package() {0x0002FFFF, 0, 0, 0x34 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||||
|
Package() {0x0004FFFF, 0, 0, 0x34 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 7 - PCIe Bridge */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
|
||||||
|
|
||||||
|
/* Bus 0, Dev 9 - PCIe Bridge */
|
||||||
|
|
||||||
|
/* Bus 0, Dev A - PCIe Bridge */
|
||||||
|
|
||||||
|
/* Bus 0, Dev B - PCIe Bridge */
|
||||||
|
Package() {0x000BFFFF, 0, 0, 0x36 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev C - PCIe Bridge */
|
||||||
|
Package() {0x000CFFFF, 0, 0, 0x36 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/
|
||||||
|
Package() {0x000DFFFF, 0, 0, 0x36 },
|
||||||
|
|
||||||
|
/* SB devices in APIC mode */
|
||||||
|
/* Bus 0, Dev 17 - SATA controller */
|
||||||
|
Package() {0x0011FFFF, 0, 0, 0x16 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||||
|
* EHCI, dev 18, 19 func 2 */
|
||||||
|
Package( ){0x0012FFFF, 0, 0, 16 },
|
||||||
|
Package() {0x0012FFFF, 1, 0, 17 },
|
||||||
|
Package() {0x0012FFFF, 2, 0, 18 },
|
||||||
|
Package() {0x0012FFFF, 3, 0, 19 },
|
||||||
|
|
||||||
|
Package() {0x0013FFFF, 0, 0, 18 },
|
||||||
|
Package() {0x0013FFFF, 1, 0, 19 },
|
||||||
|
Package() {0x0013FFFF, 2, 0, 16 },
|
||||||
|
Package() {0x0013FFFF, 3, 0, 17 },
|
||||||
|
|
||||||
|
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||||
|
Package() {0x0014FFFF, 0, 0, 16 },
|
||||||
|
Package() {0x0014FFFF, 1, 0, 17 },
|
||||||
|
Package() {0x0014FFFF, 2, 0, 18 },
|
||||||
|
Package() {0x0014FFFF, 3, 0, 19 },
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(PS2, Package(){
|
||||||
|
/* The external GFX - Hooked to PCIe slot 4 */
|
||||||
|
Package() {0x0000FFFF, 0, INTC, 0 },
|
||||||
|
Package() {0x0000FFFF, 1, INTD, 0 },
|
||||||
|
Package() {0x0000FFFF, 2, INTA, 0 },
|
||||||
|
Package() {0x0000FFFF, 3, INTB, 0 },
|
||||||
|
})
|
||||||
|
Name(APS2, Package(){
|
||||||
|
/* The external GFX - Hooked to PCIe slot 4 */
|
||||||
|
Package(){0x0000FFFF, 0, 0, 0x18 },
|
||||||
|
Package(){0x0000FFFF, 1, 0, 0x19 },
|
||||||
|
Package(){0x0000FFFF, 2, 0, 0x1A },
|
||||||
|
Package(){0x0000FFFF, 3, 0, 0x1B },
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(PS4, Package(){
|
||||||
|
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||||
|
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||||
|
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||||
|
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||||
|
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||||
|
})
|
||||||
|
Name(APS4, Package(){
|
||||||
|
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||||
|
Package(){0x0000FFFF, 0, 0, 0x2C },
|
||||||
|
Package(){0x0000FFFF, 1, 0, 0x2D },
|
||||||
|
Package(){0x0000FFFF, 2, 0, 0x2E },
|
||||||
|
Package(){0x0000FFFF, 3, 0, 0x2F },
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(PSb, Package(){
|
||||||
|
/* PCIe slot - Hooked to PCIe slot 11 */
|
||||||
|
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||||
|
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||||
|
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||||
|
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||||
|
})
|
||||||
|
Name(APSb, Package(){
|
||||||
|
/* PCIe slot - Hooked to PCIe */
|
||||||
|
Package(){0x0000FFFF, 0, 0, 0x20 },
|
||||||
|
Package(){0x0000FFFF, 1, 0, 0x21 },
|
||||||
|
Package(){0x0000FFFF, 2, 0, 0x22 },
|
||||||
|
Package(){0x0000FFFF, 3, 0, 0x23 },
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(PSc, Package(){
|
||||||
|
/* PCIe slot - Hooked to PCIe slot 12 */
|
||||||
|
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||||
|
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||||
|
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||||
|
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||||
|
})
|
||||||
|
Name(APSc, Package(){
|
||||||
|
/* PCIe slot - Hooked to PCIe */
|
||||||
|
Package(){0x0000FFFF, 0, 0, 0x24 },
|
||||||
|
Package(){0x0000FFFF, 1, 0, 0x25 },
|
||||||
|
Package(){0x0000FFFF, 2, 0, 0x26 },
|
||||||
|
Package(){0x0000FFFF, 3, 0, 0x27 },
|
||||||
|
})
|
||||||
|
|
||||||
|
Name(PSd, Package(){
|
||||||
|
/* PCIe slot - Hooked to PCIe slot 13 */
|
||||||
|
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||||
|
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||||
|
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||||
|
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||||
|
})
|
||||||
|
Name(APSd, Package(){
|
||||||
|
/* PCIe slot - Hooked to PCIe */
|
||||||
|
Package(){0x0000FFFF, 0, 0, 0x28 },
|
||||||
|
Package(){0x0000FFFF, 1, 0, 0x29 },
|
||||||
|
Package(){0x0000FFFF, 2, 0, 0x2A },
|
||||||
|
Package(){0x0000FFFF, 3, 0, 0x2B },
|
||||||
|
})
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,149 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* simple name description */
|
||||||
|
|
||||||
|
/*
|
||||||
|
Scope (_SB) {
|
||||||
|
Device(PCI0) {
|
||||||
|
Device(SATA) {
|
||||||
|
Name(_ADR, 0x00110000)
|
||||||
|
#include "sata.asl"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
|
||||||
|
Name(STTM, Buffer(20) {
|
||||||
|
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||||
|
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||||
|
0x1f, 0x00, 0x00, 0x00
|
||||||
|
})
|
||||||
|
|
||||||
|
/* Start by clearing the PhyRdyChg bits */
|
||||||
|
Method(_INI) {
|
||||||
|
\_GPE._L1F()
|
||||||
|
}
|
||||||
|
|
||||||
|
Device(PMRY)
|
||||||
|
{
|
||||||
|
Name(_ADR, 0)
|
||||||
|
Method(_GTM, 0x0, NotSerialized) {
|
||||||
|
Return(STTM)
|
||||||
|
}
|
||||||
|
Method(_STM, 0x3, NotSerialized) {}
|
||||||
|
|
||||||
|
Device(PMST) {
|
||||||
|
Name(_ADR, 0)
|
||||||
|
Method(_STA,0) {
|
||||||
|
if (LGreater(P0IS,0)) {
|
||||||
|
return (0x0F) /* sata is visible */
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
return (0x00) /* sata is missing */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}/* end of PMST */
|
||||||
|
|
||||||
|
Device(PSLA)
|
||||||
|
{
|
||||||
|
Name(_ADR, 1)
|
||||||
|
Method(_STA,0) {
|
||||||
|
if (LGreater(P1IS,0)) {
|
||||||
|
return (0x0F) /* sata is visible */
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
return (0x00) /* sata is missing */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} /* end of PSLA */
|
||||||
|
} /* end of PMRY */
|
||||||
|
|
||||||
|
|
||||||
|
Device(SEDY)
|
||||||
|
{
|
||||||
|
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||||
|
Method(_GTM, 0x0, NotSerialized) {
|
||||||
|
Return(STTM)
|
||||||
|
}
|
||||||
|
Method(_STM, 0x3, NotSerialized) {}
|
||||||
|
|
||||||
|
Device(SMST)
|
||||||
|
{
|
||||||
|
Name(_ADR, 0)
|
||||||
|
Method(_STA,0) {
|
||||||
|
if (LGreater(P2IS,0)) {
|
||||||
|
return (0x0F) /* sata is visible */
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
return (0x00) /* sata is missing */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} /* end of SMST */
|
||||||
|
|
||||||
|
Device(SSLA)
|
||||||
|
{
|
||||||
|
Name(_ADR, 1)
|
||||||
|
Method(_STA,0) {
|
||||||
|
if (LGreater(P3IS,0)) {
|
||||||
|
return (0x0F) /* sata is visible */
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
return (0x00) /* sata is missing */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} /* end of SSLA */
|
||||||
|
} /* end of SEDY */
|
||||||
|
|
||||||
|
/* SATA Hot Plug Support */
|
||||||
|
Scope(\_GPE) {
|
||||||
|
Method(_L1F,0x0,NotSerialized) {
|
||||||
|
if (\_SB.P0PR) {
|
||||||
|
if (LGreater(\_SB.P0IS,0)) {
|
||||||
|
sleep(32)
|
||||||
|
}
|
||||||
|
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||||
|
store(one, \_SB.P0PR)
|
||||||
|
}
|
||||||
|
|
||||||
|
if (\_SB.P1PR) {
|
||||||
|
if (LGreater(\_SB.P1IS,0)) {
|
||||||
|
sleep(32)
|
||||||
|
}
|
||||||
|
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||||
|
store(one, \_SB.P1PR)
|
||||||
|
}
|
||||||
|
|
||||||
|
if (\_SB.P2PR) {
|
||||||
|
if (LGreater(\_SB.P2IS,0)) {
|
||||||
|
sleep(32)
|
||||||
|
}
|
||||||
|
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||||
|
store(one, \_SB.P2PR)
|
||||||
|
}
|
||||||
|
|
||||||
|
if (\_SB.P3PR) {
|
||||||
|
if (LGreater(\_SB.P3IS,0)) {
|
||||||
|
sleep(32)
|
||||||
|
}
|
||||||
|
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||||
|
store(one, \_SB.P3PR)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,161 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* simple name description */
|
||||||
|
/*
|
||||||
|
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||||
|
)
|
||||||
|
{
|
||||||
|
#include "usb.asl"
|
||||||
|
}
|
||||||
|
*/
|
||||||
|
Method(UCOC, 0) {
|
||||||
|
Sleep(20)
|
||||||
|
Store(0x13,CMTI)
|
||||||
|
Store(0,GPSL)
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||||
|
If(LLessEqual(UOM0,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
Method (_L13) {
|
||||||
|
UCOC()
|
||||||
|
if(LEqual(GPB0,PLC0)) {
|
||||||
|
Not(PLC0,PLC0)
|
||||||
|
Store(PLC0, \_SB.PT0D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||||
|
If (LLessEqual(UOM1,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
Method (_L14) {
|
||||||
|
UCOC()
|
||||||
|
if (LEqual(GPB1,PLC1)) {
|
||||||
|
Not(PLC1,PLC1)
|
||||||
|
Store(PLC1, \_SB.PT1D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||||
|
If (LLessEqual(UOM2,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
Method (_L15) {
|
||||||
|
UCOC()
|
||||||
|
if (LEqual(GPB2,PLC2)) {
|
||||||
|
Not(PLC2,PLC2)
|
||||||
|
Store(PLC2, \_SB.PT2D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||||
|
If (LLessEqual(UOM3,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
Method (_L16) {
|
||||||
|
UCOC()
|
||||||
|
if (LEqual(GPB3,PLC3)) {
|
||||||
|
Not(PLC3,PLC3)
|
||||||
|
Store(PLC3, \_SB.PT3D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||||
|
If (LLessEqual(UOM4,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
Method (_L19) {
|
||||||
|
UCOC()
|
||||||
|
if (LEqual(GPB4,PLC4)) {
|
||||||
|
Not(PLC4,PLC4)
|
||||||
|
Store(PLC4, \_SB.PT4D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||||
|
If (LLessEqual(UOM5,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
Method (_L1A) {
|
||||||
|
UCOC()
|
||||||
|
if (LEqual(GPB5,PLC5)) {
|
||||||
|
Not(PLC5,PLC5)
|
||||||
|
Store(PLC5, \_SB.PT5D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||||
|
If (LLessEqual(UOM6,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
/* Method (_L1C) { */
|
||||||
|
Method (_L06) {
|
||||||
|
UCOC()
|
||||||
|
if (LEqual(GPB6,PLC6)) {
|
||||||
|
Not(PLC6,PLC6)
|
||||||
|
Store(PLC6, \_SB.PT6D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||||
|
If (LLessEqual(UOM7,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
/* Method (_L1D) { */
|
||||||
|
Method (_L07) {
|
||||||
|
UCOC()
|
||||||
|
if (LEqual(GPB7,PLC7)) {
|
||||||
|
Not(PLC7,PLC7)
|
||||||
|
Store(PLC7, \_SB.PT7D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||||
|
If (LLessEqual(UOM8,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
Method (_L17) {
|
||||||
|
if (LEqual(G8IS,PLC8)) {
|
||||||
|
Not(PLC8,PLC8)
|
||||||
|
Store(PLC8, \_SB.PT8D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||||
|
If (LLessEqual(UOM9,9)) {
|
||||||
|
Scope (\_GPE) {
|
||||||
|
Method (_L0E) {
|
||||||
|
if (LEqual(G9IS,0)) {
|
||||||
|
Store(1,\_SB.PT9D)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,295 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <arch/acpi.h>
|
||||||
|
#include <arch/ioapic.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <cpu/x86/msr.h>
|
||||||
|
#include <cpu/amd/mtrr.h>
|
||||||
|
#include <cpu/amd/amdfam10_sysconf.h>
|
||||||
|
#include "agesawrapper.h"
|
||||||
|
|
||||||
|
#define DUMP_ACPI_TABLES 0
|
||||||
|
|
||||||
|
#if DUMP_ACPI_TABLES == 1
|
||||||
|
static void dump_mem(u32 start, u32 end)
|
||||||
|
{
|
||||||
|
|
||||||
|
u32 i;
|
||||||
|
print_debug("dump_mem:");
|
||||||
|
for (i = start; i < end; i++) {
|
||||||
|
if ((i & 0xf) == 0) {
|
||||||
|
printk(BIOS_DEBUG, "\n%08x:", i);
|
||||||
|
}
|
||||||
|
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
|
||||||
|
}
|
||||||
|
print_debug("\n");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
extern const unsigned char AmlCode[];
|
||||||
|
extern const unsigned char AmlCode_ssdt[];
|
||||||
|
|
||||||
|
|
||||||
|
unsigned long acpi_fill_mcfg(unsigned long current)
|
||||||
|
{
|
||||||
|
/* Just a dummy */
|
||||||
|
return current;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long acpi_fill_madt(unsigned long current)
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
u32 dword;
|
||||||
|
u32 gsi_base = 0;
|
||||||
|
u32 apicid_sp5100;
|
||||||
|
u32 apicid_sr5650;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AGESA v5 Apply apic enumeration rules
|
||||||
|
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
|
||||||
|
* put the local-APICs at m..z
|
||||||
|
* For systems with < 16 APICs, put the Local-APICs at 0..n and
|
||||||
|
* put the IO-APICs at (n + 1)..z
|
||||||
|
*/
|
||||||
|
#if CONFIG_MAX_CPUS >= 16
|
||||||
|
apicid_sp5100 = 0x0;
|
||||||
|
#else
|
||||||
|
apicid_sp5100 = CONFIG_MAX_CPUS + 1
|
||||||
|
#endif
|
||||||
|
apicid_sr5650 = apicid_sp5100 + 1;
|
||||||
|
|
||||||
|
/* create all subtables for processors */
|
||||||
|
current = acpi_create_madt_lapics(current);
|
||||||
|
|
||||||
|
/* Write sp5100 IOAPIC, only one */
|
||||||
|
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||||
|
apicid_sp5100,
|
||||||
|
IO_APIC_ADDR,
|
||||||
|
0
|
||||||
|
);
|
||||||
|
|
||||||
|
/* IOAPIC on rs5690 */
|
||||||
|
gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */
|
||||||
|
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
|
||||||
|
if (dev) {
|
||||||
|
pci_write_config32(dev, 0xF8, 0x1);
|
||||||
|
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
|
||||||
|
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||||
|
apicid_sr5650,
|
||||||
|
dword,
|
||||||
|
gsi_base
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
|
||||||
|
0, //BUS
|
||||||
|
0, //SOURCE
|
||||||
|
2, //gsirq
|
||||||
|
0 //flags
|
||||||
|
);
|
||||||
|
|
||||||
|
/* 0: mean bus 0--->ISA */
|
||||||
|
/* 0: PIC 0 */
|
||||||
|
/* 2: APIC 2 */
|
||||||
|
/* 5 mean: 0101 --> Edige-triggered, Active high */
|
||||||
|
|
||||||
|
/* create all subtables for processors */
|
||||||
|
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
|
||||||
|
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
|
||||||
|
/* 1: LINT1 connect to NMI */
|
||||||
|
|
||||||
|
return current;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long acpi_fill_slit(unsigned long current)
|
||||||
|
{
|
||||||
|
// Not implemented
|
||||||
|
return current;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long acpi_fill_srat(unsigned long current)
|
||||||
|
{
|
||||||
|
/* No NUMA, no SRAT */
|
||||||
|
return current;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long write_acpi_tables(unsigned long start)
|
||||||
|
{
|
||||||
|
unsigned long current;
|
||||||
|
acpi_rsdp_t *rsdp;
|
||||||
|
acpi_rsdt_t *rsdt;
|
||||||
|
//acpi_hpet_t *hpet;
|
||||||
|
acpi_madt_t *madt;
|
||||||
|
acpi_srat_t *srat;
|
||||||
|
acpi_slit_t *slit;
|
||||||
|
acpi_fadt_t *fadt;
|
||||||
|
acpi_facs_t *facs;
|
||||||
|
acpi_header_t *dsdt;
|
||||||
|
//acpi_header_t *ssdt;
|
||||||
|
|
||||||
|
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
|
||||||
|
|
||||||
|
/* Align ACPI tables to 16 bytes */
|
||||||
|
start = (start + 0x0f) & -0x10;
|
||||||
|
current = start;
|
||||||
|
|
||||||
|
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
|
||||||
|
|
||||||
|
/* We need at least an RSDP and an RSDT Table */
|
||||||
|
rsdp = (acpi_rsdp_t *) current;
|
||||||
|
current += sizeof(acpi_rsdp_t);
|
||||||
|
rsdt = (acpi_rsdt_t *) current;
|
||||||
|
current += sizeof(acpi_rsdt_t);
|
||||||
|
|
||||||
|
/* clear all table memory */
|
||||||
|
memset((void *)start, 0, current - start);
|
||||||
|
|
||||||
|
acpi_write_rsdp(rsdp, rsdt, NULL);
|
||||||
|
acpi_write_rsdt(rsdt);
|
||||||
|
|
||||||
|
/* FACS */
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * FACS\n");
|
||||||
|
facs = (acpi_facs_t *) current;
|
||||||
|
current += sizeof(acpi_facs_t);
|
||||||
|
acpi_create_facs(facs);
|
||||||
|
|
||||||
|
/* DSDT */
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * DSDT\n");
|
||||||
|
dsdt = (acpi_header_t *)current;
|
||||||
|
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
|
||||||
|
current += dsdt->length;
|
||||||
|
memcpy(dsdt, &AmlCode, dsdt->length);
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
|
||||||
|
/* FADT */
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * FADT\n");
|
||||||
|
fadt = (acpi_fadt_t *) current;
|
||||||
|
current += sizeof(acpi_fadt_t);
|
||||||
|
|
||||||
|
acpi_create_fadt(fadt, facs, dsdt);
|
||||||
|
acpi_add_table(rsdp, fadt);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We explicitly add these tables later on:
|
||||||
|
*/
|
||||||
|
#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt
|
||||||
|
current = ( current + 0x07) & -0x08;
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
|
||||||
|
hpet = (acpi_hpet_t *) current;
|
||||||
|
current += sizeof(acpi_hpet_t);
|
||||||
|
acpi_create_hpet(hpet);
|
||||||
|
acpi_add_table(rsdp, hpet);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* If we want to use HPET Timers Linux wants an MADT */
|
||||||
|
current = ( current + 0x07) & -0x08;
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
|
||||||
|
madt = (acpi_madt_t *) current;
|
||||||
|
acpi_create_madt(madt);
|
||||||
|
current += madt->header.length;
|
||||||
|
acpi_add_table(rsdp, madt);
|
||||||
|
|
||||||
|
/* SRAT */
|
||||||
|
current = ( current + 0x07) & -0x08;
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
|
||||||
|
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
|
||||||
|
if (srat != NULL) {
|
||||||
|
memcpy((void *)current, srat, srat->header.length);
|
||||||
|
srat = (acpi_srat_t *) current;
|
||||||
|
//acpi_create_srat(srat);
|
||||||
|
current += srat->header.length;
|
||||||
|
acpi_add_table(rsdp, srat);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* SLIT */
|
||||||
|
current = ( current + 0x07) & -0x08;
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
|
||||||
|
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
|
||||||
|
if (slit != NULL) {
|
||||||
|
memcpy((void *)current, slit, slit->header.length);
|
||||||
|
slit = (acpi_slit_t *) current;
|
||||||
|
//acpi_create_slit(slit);
|
||||||
|
current += slit->header.length;
|
||||||
|
acpi_add_table(rsdp, slit);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* SSDT */
|
||||||
|
/* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */
|
||||||
|
#ifdef UNUSED_CODE
|
||||||
|
current = ( current + 0x0f) & -0x10;
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
|
||||||
|
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
|
||||||
|
if (ssdt != NULL) {
|
||||||
|
memcpy(current, ssdt, ssdt->length);
|
||||||
|
ssdt = (acpi_header_t *) current;
|
||||||
|
current += ssdt->length;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
ssdt = (acpi_header_t *) current;
|
||||||
|
memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
|
||||||
|
current += ssdt->length;
|
||||||
|
memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
|
||||||
|
/* recalculate checksum */
|
||||||
|
ssdt->checksum = 0;
|
||||||
|
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
|
||||||
|
}
|
||||||
|
acpi_add_table(rsdp,ssdt);
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* DSDT */
|
||||||
|
current = ( current + 0x07) & -0x08;
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
|
||||||
|
dsdt = (acpi_header_t *)current; // it will used by fadt
|
||||||
|
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
|
||||||
|
current += dsdt->length;
|
||||||
|
memcpy(dsdt, &AmlCode, dsdt->length);
|
||||||
|
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
|
||||||
|
|
||||||
|
#if DUMP_ACPI_TABLES == 1
|
||||||
|
printk(BIOS_DEBUG, "rsdp\n");
|
||||||
|
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "rsdt\n");
|
||||||
|
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "madt\n");
|
||||||
|
dump_mem(madt, ((void *)madt) + madt->header.length);
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "srat\n");
|
||||||
|
dump_mem(srat, ((void *)srat) + srat->header.length);
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "slit\n");
|
||||||
|
dump_mem(slit, ((void *)slit) + slit->header.length);
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "ssdt\n");
|
||||||
|
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "fadt\n");
|
||||||
|
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
printk(BIOS_INFO, "ACPI: done.\n");
|
||||||
|
return current;
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,87 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------------------
|
||||||
|
* M O D U L E S U S E D
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef _AGESAWRAPPER_H_
|
||||||
|
#define _AGESAWRAPPER_H_
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include "Porting.h"
|
||||||
|
#include "AGESA.h"
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------------------
|
||||||
|
* D E F I N I T I O N S A N D M A C R O S
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
|
||||||
|
|
||||||
|
enum {
|
||||||
|
PICK_DMI, /* DMI Interface */
|
||||||
|
PICK_PSTATE, /* Acpi Pstate SSDT Table */
|
||||||
|
PICK_SRAT, /* SRAT Table */
|
||||||
|
PICK_SLIT, /* SLIT Table */
|
||||||
|
PICK_WHEA_MCE, /* WHEA MCE table */
|
||||||
|
PICK_WHEA_CMC, /* WHEA CMV table */
|
||||||
|
PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------------------
|
||||||
|
* T Y P E D E F S A N D S T R U C T U R E S
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
UINT32 CalloutName;
|
||||||
|
AGESA_STATUS (*CalloutPtr)(UINT32 Func, UINT32 Data, VOID* ConfigPtr);
|
||||||
|
} BIOS_CALLOUT_STRUCT;
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------------------
|
||||||
|
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------------------
|
||||||
|
* E X P O R T E D F U N C T I O N S
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------
|
||||||
|
* L O C A L F U N C T I O N S
|
||||||
|
*---------------------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
UINT32 agesawrapper_amdinitreset (void);
|
||||||
|
UINT32 agesawrapper_amdinitearly (void);
|
||||||
|
UINT32 agesawrapper_amdinitenv (void);
|
||||||
|
UINT32 agesawrapper_amdinitlate (void);
|
||||||
|
UINT32 agesawrapper_amdinitpost (void);
|
||||||
|
UINT32 agesawrapper_amdinitmid (void);
|
||||||
|
UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus);
|
||||||
|
UINT32 agesawrapper_amdinitmmio (void);
|
||||||
|
void *agesawrapper_getlateinitptr (int pick);
|
||||||
|
UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,541 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "AGESA.h"
|
||||||
|
#include "CommonReturns.h"
|
||||||
|
#include "AdvancedApi.h"
|
||||||
|
#include <PlatformMemoryConfiguration.h>
|
||||||
|
#include "Filecode.h"
|
||||||
|
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
|
||||||
|
|
||||||
|
/* AGESA will check the OEM configuration during preprocessing stage,
|
||||||
|
* coreboot enable -Wundef option, so we should make sure we have all contanstand defined
|
||||||
|
*/
|
||||||
|
/* MEMORY_BUS_SPEED */
|
||||||
|
#define DDR400_FREQUENCY 200 ///< DDR 400
|
||||||
|
#define DDR533_FREQUENCY 266 ///< DDR 533
|
||||||
|
#define DDR667_FREQUENCY 333 ///< DDR 667
|
||||||
|
#define DDR800_FREQUENCY 400 ///< DDR 800
|
||||||
|
#define DDR1066_FREQUENCY 533 ///< DDR 1066
|
||||||
|
#define DDR1333_FREQUENCY 667 ///< DDR 1333
|
||||||
|
#define DDR1600_FREQUENCY 800 ///< DDR 1600
|
||||||
|
#define DDR1866_FREQUENCY 933 ///< DDR 1866
|
||||||
|
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
|
||||||
|
|
||||||
|
/* QUANDRANK_TYPE*/
|
||||||
|
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
|
||||||
|
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
|
||||||
|
|
||||||
|
/* USER_MEMORY_TIMING_MODE */
|
||||||
|
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
|
||||||
|
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
|
||||||
|
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
|
||||||
|
|
||||||
|
/* POWER_DOWN_MODE */
|
||||||
|
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
|
||||||
|
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
|
||||||
|
|
||||||
|
/* User makes option selections here
|
||||||
|
* Comment out the items wanted to be included in the build.
|
||||||
|
* Uncomment those items you with to REMOVE from the build.
|
||||||
|
*/
|
||||||
|
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
|
||||||
|
//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
|
||||||
|
//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
|
||||||
|
//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
|
||||||
|
//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
|
||||||
|
//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
|
||||||
|
//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
|
||||||
|
//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
|
||||||
|
#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
|
||||||
|
//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
|
||||||
|
////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE
|
||||||
|
////#define BLDOPT_REMOVE_SRAT TRUE
|
||||||
|
////#define BLDOPT_REMOVE_SLIT TRUE
|
||||||
|
//#define BLDOPT_REMOVE_WHEA TRUE
|
||||||
|
//#define BLDOPT_REMOVE_DMI TRUE
|
||||||
|
//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
|
||||||
|
//#define BLDOPT_REMOVE_HT_ASSIST TRUE
|
||||||
|
//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
|
||||||
|
//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
|
||||||
|
//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
|
||||||
|
//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
|
||||||
|
//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
|
||||||
|
//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
|
||||||
|
|
||||||
|
/* Build configuration values here.
|
||||||
|
*/
|
||||||
|
#define BLDCFG_VRM_CURRENT_LIMIT 120000
|
||||||
|
#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
|
||||||
|
#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
|
||||||
|
#define BLDCFG_PLAT_NUM_IO_APICS 3
|
||||||
|
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
|
||||||
|
#define BLDCFG_MEM_INIT_PSTATE 0
|
||||||
|
#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
|
||||||
|
|
||||||
|
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
|
||||||
|
|
||||||
|
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600
|
||||||
|
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
|
||||||
|
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
|
||||||
|
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
|
||||||
|
#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
|
||||||
|
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
|
||||||
|
#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
|
||||||
|
#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
|
||||||
|
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE
|
||||||
|
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE
|
||||||
|
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE
|
||||||
|
#define BLDCFG_MEMORY_POWER_DOWN FALSE
|
||||||
|
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL
|
||||||
|
#define BLDCFG_ONLINE_SPARE FALSE
|
||||||
|
#define BLDCFG_BANK_SWIZZLE TRUE
|
||||||
|
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
|
||||||
|
#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
|
||||||
|
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
|
||||||
|
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
|
||||||
|
#define BLDCFG_USE_BURST_MODE FALSE
|
||||||
|
#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
|
||||||
|
#define BLDCFG_ENABLE_ECC_FEATURE TRUE
|
||||||
|
#define BLDCFG_ECC_REDIRECTION FALSE
|
||||||
|
#define BLDCFG_SCRUB_IC_RATE 0
|
||||||
|
#define BLDCFG_ECC_SYNC_FLOOD TRUE
|
||||||
|
#define BLDCFG_ECC_SYMBOL_SIZE 4
|
||||||
|
|
||||||
|
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
|
||||||
|
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Enable Message Based C1e CPU feature in multi-socket systems.
|
||||||
|
* BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
|
||||||
|
* else the feature cannot be enabled.
|
||||||
|
*/
|
||||||
|
#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased
|
||||||
|
#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO
|
||||||
|
//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
|
||||||
|
//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
|
||||||
|
|
||||||
|
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
|
||||||
|
#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
|
||||||
|
#define BLDCFG_1GB_ALIGN FALSE
|
||||||
|
//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
|
||||||
|
//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
|
||||||
|
//
|
||||||
|
|
||||||
|
// Select the platform control flow mode for performance tuning.
|
||||||
|
#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Enable the probe filtering performance tuning feature.
|
||||||
|
* The probe filter provides filtering of broadcast probes to
|
||||||
|
* improve link bandwidth and performance for multi- node systems.
|
||||||
|
*
|
||||||
|
* This feature may interact with other performance features.
|
||||||
|
* TRUE -Enable the feature (default) if supported by all processors,
|
||||||
|
* based on revision and presence of L3 cache.
|
||||||
|
* The feature is not enabled if there are no coherent HT links.
|
||||||
|
* FALSE -Do not enable the feature regardless of the configuration.
|
||||||
|
*/
|
||||||
|
//TODO enable it,
|
||||||
|
//but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
|
||||||
|
//hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
|
||||||
|
#define BLDCFG_USE_HT_ASSIST FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* The socket and link match values are platform specific
|
||||||
|
*/
|
||||||
|
CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] =
|
||||||
|
{
|
||||||
|
{
|
||||||
|
/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
|
||||||
|
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
|
||||||
|
|
||||||
|
{ //BUID Swap List
|
||||||
|
{ //BUID Swaps
|
||||||
|
/* Each Non-coherent chain may have a list of device swaps,
|
||||||
|
* Each item specify a device will be swap from its current id to a new one
|
||||||
|
*/
|
||||||
|
/* FromID 0x00 is the chain with the southbridge */
|
||||||
|
/* 'Move' device zero to device zero, All others are non applicable */
|
||||||
|
{0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
|
||||||
|
{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
|
||||||
|
{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
|
||||||
|
{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
|
||||||
|
{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
|
||||||
|
{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
|
||||||
|
{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
|
||||||
|
{0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
|
||||||
|
},
|
||||||
|
|
||||||
|
{ //The ordered final BUIDs
|
||||||
|
/* Specify the final BUID to be zero, All others are non applicable */
|
||||||
|
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
|
||||||
|
/* The 2nd element in the array merely terminates the list */
|
||||||
|
{
|
||||||
|
HT_LIST_TERMINAL,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
#if CONFIG_HT3_SUPPORT == 1
|
||||||
|
/**
|
||||||
|
* The socket and link match values are platform specific
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
|
||||||
|
{
|
||||||
|
{
|
||||||
|
/* On the reference platform, these settings apply to all coherent links */
|
||||||
|
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
|
||||||
|
|
||||||
|
/* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
|
||||||
|
HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
|
||||||
|
},
|
||||||
|
|
||||||
|
/* The 2nd element in the array merely terminates the list */
|
||||||
|
{
|
||||||
|
HT_LIST_TERMINAL,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
|
||||||
|
{
|
||||||
|
{
|
||||||
|
/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
|
||||||
|
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
|
||||||
|
|
||||||
|
/* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
|
||||||
|
HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
|
||||||
|
},
|
||||||
|
|
||||||
|
/* The 2nd element in the array merely terminates the list */
|
||||||
|
{
|
||||||
|
HT_LIST_TERMINAL,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
#else //CONFIG_HT3_SUPPORT == 0
|
||||||
|
CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
|
||||||
|
{
|
||||||
|
{
|
||||||
|
/* On the reference platform, these settings apply to all coherent links */
|
||||||
|
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
|
||||||
|
|
||||||
|
/* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
|
||||||
|
HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
|
||||||
|
},
|
||||||
|
|
||||||
|
/* The 2nd element in the array merely terminates the list */
|
||||||
|
{
|
||||||
|
HT_LIST_TERMINAL,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
|
||||||
|
{
|
||||||
|
{
|
||||||
|
/* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
|
||||||
|
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
|
||||||
|
|
||||||
|
/* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
|
||||||
|
HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
|
||||||
|
},
|
||||||
|
|
||||||
|
/* The 2nd element in the array merely terminates the list */
|
||||||
|
{
|
||||||
|
HT_LIST_TERMINAL
|
||||||
|
}
|
||||||
|
};
|
||||||
|
#endif //CONFIG_HT3_SUPPORT == 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* HyperTransport links will typically require an equalization at high frequencies.
|
||||||
|
* This is called deemphasis.
|
||||||
|
*
|
||||||
|
* Deemphasis is specified as levels, for example, -3 db.
|
||||||
|
* There are two levels for each link, its receiver deemphasis level and its DCV level,
|
||||||
|
* which is based on the far side transmitter's deemphasis.
|
||||||
|
* For each link, different levels may be required at each link frequency.
|
||||||
|
*
|
||||||
|
* Coherent connections between processors should have an entry for the port on each processor.
|
||||||
|
* There should be one entry for the host root port of each non-coherent chain.
|
||||||
|
*
|
||||||
|
* AGESA initialization code does not set deemphasis on IO Devices.
|
||||||
|
* A default is provided for internal links of MCM processors, and
|
||||||
|
* those links will generally not need deemphasis structures.
|
||||||
|
*/
|
||||||
|
CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] =
|
||||||
|
{
|
||||||
|
/* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
|
||||||
|
|
||||||
|
/* Non-coherent link deemphasis. */
|
||||||
|
{0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
|
||||||
|
{0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
|
||||||
|
{0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
|
||||||
|
{0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
|
||||||
|
{0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
|
||||||
|
{0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
|
||||||
|
|
||||||
|
/* Coherent link deemphasis. */
|
||||||
|
{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
|
||||||
|
{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
|
||||||
|
{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
|
||||||
|
{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
|
||||||
|
{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
|
||||||
|
{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
|
||||||
|
|
||||||
|
/* End of the list */
|
||||||
|
{
|
||||||
|
HT_LIST_TERMINAL
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* For systems using socket infrastructure that permits strapping the SBI
|
||||||
|
* address for each socket, this should be used to provide a socket ID value.
|
||||||
|
* This is referred to as the hardware method for socket naming, and is the
|
||||||
|
* preferred solution.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* I do NOT know howto config socket id in simnow,
|
||||||
|
* so use this software way to make HT works in simnow,
|
||||||
|
* real hardware do not need this Socket Map.
|
||||||
|
*
|
||||||
|
* A physical socket map for a 4 G34 Sockets MCM processors topology,
|
||||||
|
* reference the mainboard schemantic in detail.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] =
|
||||||
|
{
|
||||||
|
#define HT_SOCKET0 0
|
||||||
|
#define HT_SOCKET1 1
|
||||||
|
#define HT_SOCKET2 2
|
||||||
|
#define HT_SOCKET3 3
|
||||||
|
|
||||||
|
/**
|
||||||
|
* 0-3 are sublink 0, 4-7 are sublink 1
|
||||||
|
*/
|
||||||
|
#define HT_LINK0A 0
|
||||||
|
#define HT_LINK1A 1
|
||||||
|
#define HT_LINK2A 2
|
||||||
|
#define HT_LINK3A 3
|
||||||
|
#define HT_LINK0B 4
|
||||||
|
#define HT_LINK1B 5
|
||||||
|
#define HT_LINK2B 6
|
||||||
|
#define HT_LINK3B 7
|
||||||
|
|
||||||
|
/* Source Socket, Link, Target Socket */
|
||||||
|
{HT_SOCKET0, HT_LINK0A, HT_SOCKET1},
|
||||||
|
{HT_SOCKET0, HT_LINK0B, HT_SOCKET3},
|
||||||
|
{HT_SOCKET0, HT_LINK1A, HT_SOCKET1},
|
||||||
|
{HT_SOCKET0, HT_LINK1B, HT_SOCKET3},
|
||||||
|
{HT_SOCKET0, HT_LINK3A, HT_SOCKET2},
|
||||||
|
{HT_SOCKET0, HT_LINK3B, HT_SOCKET2},
|
||||||
|
|
||||||
|
{HT_SOCKET1, HT_LINK0A, HT_SOCKET2},
|
||||||
|
{HT_SOCKET1, HT_LINK0B, HT_SOCKET3},
|
||||||
|
{HT_SOCKET1, HT_LINK1A, HT_SOCKET0},
|
||||||
|
{HT_SOCKET1, HT_LINK1B, HT_SOCKET2},
|
||||||
|
{HT_SOCKET1, HT_LINK3A, HT_SOCKET0},
|
||||||
|
{HT_SOCKET1, HT_LINK3B, HT_SOCKET3},
|
||||||
|
|
||||||
|
{HT_SOCKET2, HT_LINK0A, HT_SOCKET3},
|
||||||
|
{HT_SOCKET2, HT_LINK0B, HT_SOCKET0},
|
||||||
|
{HT_SOCKET2, HT_LINK1A, HT_SOCKET3},
|
||||||
|
{HT_SOCKET2, HT_LINK1B, HT_SOCKET1},
|
||||||
|
{HT_SOCKET2, HT_LINK3A, HT_SOCKET1},
|
||||||
|
{HT_SOCKET2, HT_LINK3B, HT_SOCKET0},
|
||||||
|
|
||||||
|
{HT_SOCKET3, HT_LINK0A, HT_SOCKET2},
|
||||||
|
{HT_SOCKET3, HT_LINK0B, HT_SOCKET1},
|
||||||
|
{HT_SOCKET3, HT_LINK1A, HT_SOCKET1},
|
||||||
|
{HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
|
||||||
|
{HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
|
||||||
|
{HT_SOCKET3, HT_LINK3B, HT_SOCKET2},
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
|
||||||
|
{
|
||||||
|
{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull},
|
||||||
|
{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull},
|
||||||
|
{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull},
|
||||||
|
{AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull},
|
||||||
|
{AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull},
|
||||||
|
{AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull},
|
||||||
|
{AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull},
|
||||||
|
{AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull},
|
||||||
|
{AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull},
|
||||||
|
{AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull},
|
||||||
|
{AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull},
|
||||||
|
{CPU_LIST_TERMINAL}
|
||||||
|
};
|
||||||
|
|
||||||
|
#define BLDCFG_BUID_SWAP_LIST &h8qgi_manual_swaplist
|
||||||
|
#define BLDCFG_HTFABRIC_LIMITS_LIST &h8qgi_cpu2cpu_limit_list
|
||||||
|
#define BLDCFG_HTCHAIN_LIMITS_LIST &h8qgi_io_limit_list
|
||||||
|
#define BLDCFG_PLATFORM_DEEMPHASIS_LIST &h8qgi_deemphasis_list
|
||||||
|
#define BLDCFG_AP_MTRR_SETTINGS_LIST &h8qgi_ap_mtrr_list
|
||||||
|
//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &h8qgi_socket_map
|
||||||
|
|
||||||
|
|
||||||
|
/* Process the options...
|
||||||
|
* This file include MUST occur AFTER the user option selection settings
|
||||||
|
*/
|
||||||
|
#define AGESA_ENTRY_INIT_RESET FALSE//TRUE
|
||||||
|
#define AGESA_ENTRY_INIT_RECOVERY FALSE
|
||||||
|
#define AGESA_ENTRY_INIT_EARLY TRUE
|
||||||
|
#define AGESA_ENTRY_INIT_POST TRUE
|
||||||
|
#define AGESA_ENTRY_INIT_ENV TRUE
|
||||||
|
#define AGESA_ENTRY_INIT_MID TRUE
|
||||||
|
#define AGESA_ENTRY_INIT_LATE TRUE
|
||||||
|
#define AGESA_ENTRY_INIT_S3SAVE TRUE
|
||||||
|
#define AGESA_ENTRY_INIT_RESUME TRUE
|
||||||
|
#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
|
||||||
|
#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
|
||||||
|
|
||||||
|
#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/
|
||||||
|
#include "MaranelloInstall.h"
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------------------
|
||||||
|
* CUSTOMER OVERIDES MEMORY TABLE
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||||
|
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||||
|
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||||
|
* use its default conservative settings.
|
||||||
|
*/
|
||||||
|
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
|
||||||
|
//
|
||||||
|
// The following macros are supported (use comma to separate macros):
|
||||||
|
//
|
||||||
|
// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
|
||||||
|
// The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
|
||||||
|
// AGESA will base on this value to disable unused MemClk to save power.
|
||||||
|
// Example:
|
||||||
|
// BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
|
||||||
|
// Bit AM3/S1g3 pin name
|
||||||
|
// 0 M[B,A]_CLK_H/L[0]
|
||||||
|
// 1 M[B,A]_CLK_H/L[1]
|
||||||
|
// 2 M[B,A]_CLK_H/L[2]
|
||||||
|
// 3 M[B,A]_CLK_H/L[3]
|
||||||
|
// 4 M[B,A]_CLK_H/L[4]
|
||||||
|
// 5 M[B,A]_CLK_H/L[5]
|
||||||
|
// 6 M[B,A]_CLK_H/L[6]
|
||||||
|
// 7 M[B,A]_CLK_H/L[7]
|
||||||
|
// And platform has the following routing:
|
||||||
|
// CS0 M[B,A]_CLK_H/L[4]
|
||||||
|
// CS1 M[B,A]_CLK_H/L[2]
|
||||||
|
// CS2 M[B,A]_CLK_H/L[3]
|
||||||
|
// CS3 M[B,A]_CLK_H/L[5]
|
||||||
|
// Then platform can specify the following macro:
|
||||||
|
// MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
|
||||||
|
//
|
||||||
|
// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
|
||||||
|
// The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
|
||||||
|
// AGESA will base on this value to tristate unused CKE to save power.
|
||||||
|
//
|
||||||
|
// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
|
||||||
|
// The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
|
||||||
|
// AGESA will base on this value to tristate unused ODT pins to save power.
|
||||||
|
//
|
||||||
|
// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
|
||||||
|
// The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
|
||||||
|
// AGESA will base on this value to tristate unused Chip select to save power.
|
||||||
|
//
|
||||||
|
// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
|
||||||
|
// Specifies the number of DIMM slots per channel.
|
||||||
|
//
|
||||||
|
// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
|
||||||
|
// Specifies the number of Chip selects per channel.
|
||||||
|
//
|
||||||
|
// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
|
||||||
|
// Specifies the number of channels per socket.
|
||||||
|
//
|
||||||
|
// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
|
||||||
|
// Specifies DDR bus speed of channel ChannelID on socket SocketID.
|
||||||
|
//
|
||||||
|
// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
|
||||||
|
// Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
|
||||||
|
//
|
||||||
|
// WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
|
||||||
|
// Byte6Seed, Byte7Seed, ByteEccSeed)
|
||||||
|
// Specifies the write leveling seed for a channel of a socket.
|
||||||
|
//
|
||||||
|
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
|
||||||
|
PSO_END
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* These tables are optional and may be used to adjust memory timing settings
|
||||||
|
*/
|
||||||
|
|
||||||
|
//HY Customer table
|
||||||
|
UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] =
|
||||||
|
{
|
||||||
|
// Hardcoded Memory Training Values
|
||||||
|
|
||||||
|
// The following macro should be used to override training values for your platform
|
||||||
|
//
|
||||||
|
// DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
|
||||||
|
//
|
||||||
|
// NOTE:
|
||||||
|
// The following training hardcode values are example values that were taken from a tilapia motherboard
|
||||||
|
// with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
|
||||||
|
// the table and replace the byte lane values with your own.
|
||||||
|
//
|
||||||
|
// ------------------ BYTE LANES ----------------------
|
||||||
|
// BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
|
||||||
|
// Write Data Timing
|
||||||
|
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
|
||||||
|
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
|
||||||
|
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
|
||||||
|
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
|
||||||
|
|
||||||
|
// DQS Receiver Enable
|
||||||
|
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
|
||||||
|
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
|
||||||
|
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
|
||||||
|
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
|
||||||
|
|
||||||
|
// Write DQS Delays
|
||||||
|
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
|
||||||
|
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
|
||||||
|
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
|
||||||
|
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
|
||||||
|
|
||||||
|
// Read DQS Delays
|
||||||
|
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
|
||||||
|
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
|
||||||
|
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
|
||||||
|
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
|
||||||
|
//--------------------------------------------------------------------------------------------------------------------------------------------------
|
||||||
|
// TABLE END
|
||||||
|
NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
|
||||||
|
};
|
||||||
|
UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);
|
||||||
|
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
extern struct chip_operations mainboard_ops;
|
||||||
|
|
||||||
|
struct mainboard_config {};
|
||||||
|
|
@ -0,0 +1,118 @@
|
||||||
|
#*****************************************************************************
|
||||||
|
#
|
||||||
|
# This file is part of the coreboot project.
|
||||||
|
#
|
||||||
|
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or modify
|
||||||
|
# it under the terms of the GNU General Public License as published by
|
||||||
|
# the Free Software Foundation; version 2 of the License.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
#*****************************************************************************
|
||||||
|
|
||||||
|
entries
|
||||||
|
|
||||||
|
#start-bit length config config-ID name
|
||||||
|
#0 8 r 0 seconds
|
||||||
|
#8 8 r 0 alarm_seconds
|
||||||
|
#16 8 r 0 minutes
|
||||||
|
#24 8 r 0 alarm_minutes
|
||||||
|
#32 8 r 0 hours
|
||||||
|
#40 8 r 0 alarm_hours
|
||||||
|
#48 8 r 0 day_of_week
|
||||||
|
#56 8 r 0 day_of_month
|
||||||
|
#64 8 r 0 month
|
||||||
|
#72 8 r 0 year
|
||||||
|
#80 4 r 0 rate_select
|
||||||
|
#84 3 r 0 REF_Clock
|
||||||
|
#87 1 r 0 UIP
|
||||||
|
#88 1 r 0 auto_switch_DST
|
||||||
|
#89 1 r 0 24_hour_mode
|
||||||
|
#90 1 r 0 binary_values_enable
|
||||||
|
#91 1 r 0 square-wave_out_enable
|
||||||
|
#92 1 r 0 update_finished_enable
|
||||||
|
#93 1 r 0 alarm_interrupt_enable
|
||||||
|
#94 1 r 0 periodic_interrupt_enable
|
||||||
|
#95 1 r 0 disable_clock_updates
|
||||||
|
#96 288 r 0 temporary_filler
|
||||||
|
0 384 r 0 reserved_memory
|
||||||
|
384 1 e 4 boot_option
|
||||||
|
385 1 e 4 last_boot
|
||||||
|
386 1 e 1 ECC_memory
|
||||||
|
388 4 r 0 reboot_bits
|
||||||
|
392 3 e 5 baud_rate
|
||||||
|
395 1 e 1 hw_scrubber
|
||||||
|
396 1 e 1 interleave_chip_selects
|
||||||
|
397 2 e 8 max_mem_clock
|
||||||
|
399 1 e 2 multi_core
|
||||||
|
400 1 e 1 power_on_after_fail
|
||||||
|
412 4 e 6 debug_level
|
||||||
|
416 4 e 7 boot_first
|
||||||
|
420 4 e 7 boot_second
|
||||||
|
424 4 e 7 boot_third
|
||||||
|
428 4 h 0 boot_index
|
||||||
|
432 8 h 0 boot_countdown
|
||||||
|
440 4 e 9 slow_cpu
|
||||||
|
444 1 e 1 nmi
|
||||||
|
445 1 e 1 iommu
|
||||||
|
728 256 h 0 user_data
|
||||||
|
984 16 h 0 check_sum
|
||||||
|
# Reserve the extended AMD configuration registers
|
||||||
|
1000 24 r 0 amd_reserved
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
enumerations
|
||||||
|
|
||||||
|
#ID value text
|
||||||
|
1 0 Disable
|
||||||
|
1 1 Enable
|
||||||
|
2 0 Enable
|
||||||
|
2 1 Disable
|
||||||
|
4 0 Fallback
|
||||||
|
4 1 Normal
|
||||||
|
5 0 115200
|
||||||
|
5 1 57600
|
||||||
|
5 2 38400
|
||||||
|
5 3 19200
|
||||||
|
5 4 9600
|
||||||
|
5 5 4800
|
||||||
|
5 6 2400
|
||||||
|
5 7 1200
|
||||||
|
6 6 Notice
|
||||||
|
6 7 Info
|
||||||
|
6 8 Debug
|
||||||
|
6 9 Spew
|
||||||
|
7 0 Network
|
||||||
|
7 1 HDD
|
||||||
|
7 2 Floppy
|
||||||
|
7 8 Fallback_Network
|
||||||
|
7 9 Fallback_HDD
|
||||||
|
7 10 Fallback_Floppy
|
||||||
|
#7 3 ROM
|
||||||
|
8 0 400Mhz
|
||||||
|
8 1 333Mhz
|
||||||
|
8 2 266Mhz
|
||||||
|
8 3 200Mhz
|
||||||
|
9 0 off
|
||||||
|
9 1 87.5%
|
||||||
|
9 2 75.0%
|
||||||
|
9 3 62.5%
|
||||||
|
9 4 50.0%
|
||||||
|
9 5 37.5%
|
||||||
|
9 6 25.0%
|
||||||
|
9 7 12.5%
|
||||||
|
|
||||||
|
checksums
|
||||||
|
|
||||||
|
checksum 392 983 984
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,176 @@
|
||||||
|
#
|
||||||
|
# This file is part of the coreboot project.
|
||||||
|
#
|
||||||
|
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or modify
|
||||||
|
# it under the terms of the GNU General Public License as published by
|
||||||
|
# the Free Software Foundation; version 2 of the License.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
#
|
||||||
|
chip northbridge/amd/agesa/family10/root_complex
|
||||||
|
device lapic_cluster 0 on
|
||||||
|
chip cpu/amd/agesa/family10
|
||||||
|
device lapic 0x10 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device pci_domain 0 on
|
||||||
|
subsystemid 0x15d9 0xab11 inherit #SuperMicro
|
||||||
|
chip northbridge/amd/agesa/family10 # CPU side of HT root complex
|
||||||
|
device pci 18.0 on end # link 0
|
||||||
|
device pci 18.0 on end # link 1
|
||||||
|
device pci 18.0 on end # link 2
|
||||||
|
device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3
|
||||||
|
chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex
|
||||||
|
device pci 0.0 on end # HT Root Complex 0x9600
|
||||||
|
device pci 0.1 off end # CLKCONFIG
|
||||||
|
device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16
|
||||||
|
device pci 3.0 off end # GPP1 Port1
|
||||||
|
device pci 4.0 off end # GPP3a Port0 x4 SAS
|
||||||
|
device pci 5.0 off end # GPP3a Port1
|
||||||
|
device pci 6.0 off end # GPP3a Port2
|
||||||
|
device pci 7.0 off end # GPP3a Port3
|
||||||
|
device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
|
||||||
|
device pci 9.0 off end # GPP3a Port4 x1 NC
|
||||||
|
device pci a.0 off end # GPP3a Port5 x1 NC
|
||||||
|
device pci b.0 off end # GPP2 Port0 (Not for sr5650)
|
||||||
|
device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
|
||||||
|
device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
|
||||||
|
register "gpp1_configuration" = "0" # Configuration 16:0 default
|
||||||
|
register "gpp2_configuration" = "1" # Configuration 8:8
|
||||||
|
register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
|
||||||
|
#register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1
|
||||||
|
register "port_enable" = "0x2104"
|
||||||
|
end #southbridge/amd/sr5650
|
||||||
|
chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus
|
||||||
|
device pci 11.0 on end # SATA
|
||||||
|
device pci 12.0 on end # USB1
|
||||||
|
device pci 12.1 on end # USB1
|
||||||
|
device pci 12.2 on end # USB1
|
||||||
|
device pci 13.0 on end # USB2
|
||||||
|
device pci 13.1 on end # USB2
|
||||||
|
device pci 13.2 on end # USB2
|
||||||
|
device pci 14.0 on end # SM
|
||||||
|
device pci 14.1 on end # IDE 0x439c
|
||||||
|
device pci 14.2 off end # HDA 0x4383, h8qgi doesnt have codec.
|
||||||
|
device pci 14.3 on # LPC 0x439d
|
||||||
|
chip superio/winbond/w83627dhg
|
||||||
|
device pnp 2e.0 off # Floppy
|
||||||
|
io 0x60 = 0x3f0
|
||||||
|
irq 0x70 = 6
|
||||||
|
drq 0x74 = 2
|
||||||
|
end
|
||||||
|
device pnp 2e.1 off # Parallel Port
|
||||||
|
io 0x60 = 0x378
|
||||||
|
irq 0x70 = 7
|
||||||
|
end
|
||||||
|
device pnp 2e.2 on # Com1
|
||||||
|
io 0x60 = 0x3f8
|
||||||
|
irq 0x70 = 4
|
||||||
|
end
|
||||||
|
device pnp 2e.3 on # Com2
|
||||||
|
io 0x60 = 0x2f8
|
||||||
|
irq 0x70 = 3
|
||||||
|
end
|
||||||
|
## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS##
|
||||||
|
device pnp 2e.5 on # PS/2 keyboard & mouse
|
||||||
|
io 0x60 = 0x60
|
||||||
|
io 0x62 = 0x64
|
||||||
|
irq 0x70 = 0x01 #keyboard
|
||||||
|
irq 0x72 = 0x0C #mouse
|
||||||
|
end
|
||||||
|
#device pnp 2e.6 off # SPI
|
||||||
|
#end
|
||||||
|
device pnp 2e.307 off # GPIO6
|
||||||
|
end
|
||||||
|
device pnp 2e.8 off # WDTO#, PLED
|
||||||
|
end
|
||||||
|
device pnp 2e.009 off # GPIO2
|
||||||
|
end
|
||||||
|
device pnp 2e.109 off # GPIO3
|
||||||
|
end
|
||||||
|
device pnp 2e.209 off # GPIO4
|
||||||
|
end
|
||||||
|
device pnp 2e.309 off # GPIO5
|
||||||
|
end
|
||||||
|
device pnp 2e.a off # ACPI
|
||||||
|
end
|
||||||
|
device pnp 2e.b off # HWM
|
||||||
|
io 0x60 = 0x290
|
||||||
|
end
|
||||||
|
device pnp 2e.c off # PECI, SST
|
||||||
|
end
|
||||||
|
end #superio/winbond/w83627dhg
|
||||||
|
end # LPC
|
||||||
|
device pci 14.4 on end # PCI 0x4384
|
||||||
|
device pci 14.5 on end # USB 3
|
||||||
|
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||||
|
end # southbridge/amd/sp5100
|
||||||
|
end # device pci 18.0
|
||||||
|
|
||||||
|
device pci 18.1 on end
|
||||||
|
device pci 18.2 on end
|
||||||
|
device pci 18.3 on end
|
||||||
|
device pci 18.4 on end
|
||||||
|
|
||||||
|
device pci 19.0 on end
|
||||||
|
device pci 19.1 on end
|
||||||
|
device pci 19.2 on end
|
||||||
|
device pci 19.3 on end
|
||||||
|
device pci 19.4 on end
|
||||||
|
|
||||||
|
|
||||||
|
device pci 1a.0 on end
|
||||||
|
device pci 1a.0 on end
|
||||||
|
device pci 1a.0 on end
|
||||||
|
device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3
|
||||||
|
end
|
||||||
|
device pci 1a.1 on end
|
||||||
|
device pci 1a.2 on end
|
||||||
|
device pci 1a.3 on end
|
||||||
|
device pci 1a.4 on end
|
||||||
|
|
||||||
|
device pci 1b.0 on end
|
||||||
|
device pci 1b.1 on end
|
||||||
|
device pci 1b.2 on end
|
||||||
|
device pci 1b.3 on end
|
||||||
|
device pci 1b.4 on end
|
||||||
|
|
||||||
|
|
||||||
|
device pci 1c.0 on end
|
||||||
|
device pci 1c.1 on end
|
||||||
|
device pci 1c.2 on end
|
||||||
|
device pci 1c.3 on end
|
||||||
|
device pci 1c.4 on end
|
||||||
|
|
||||||
|
device pci 1d.0 on end
|
||||||
|
device pci 1d.1 on end
|
||||||
|
device pci 1d.2 on end
|
||||||
|
device pci 1d.3 on end
|
||||||
|
device pci 1d.4 on end
|
||||||
|
|
||||||
|
|
||||||
|
device pci 1e.0 on end
|
||||||
|
device pci 1e.1 on end
|
||||||
|
device pci 1e.2 on end
|
||||||
|
device pci 1e.3 on end
|
||||||
|
device pci 1e.4 on end
|
||||||
|
|
||||||
|
device pci 1f.0 on end
|
||||||
|
device pci 1f.1 on end
|
||||||
|
device pci 1f.2 on end
|
||||||
|
device pci 1f.3 on end
|
||||||
|
device pci 1f.4 on end
|
||||||
|
|
||||||
|
end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex
|
||||||
|
end #pci_domain
|
||||||
|
end #northbridge/amd/agesa/family10/root_complex
|
||||||
|
|
||||||
|
|
@ -0,0 +1,229 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "Porting.h"
|
||||||
|
#include "AGESA.h"
|
||||||
|
#include "amdlib.h"
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <arch/romcc_io.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
|
||||||
|
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
|
||||||
|
#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
|
||||||
|
|
||||||
|
/* SP5100 GPIO 53-56 contoled by SMBUS PCI_Reg 0x52 */
|
||||||
|
#define SP5100_GPIO53_56 0x52
|
||||||
|
|
||||||
|
/**
|
||||||
|
* TODO not support all GPIO yet
|
||||||
|
* @param reg -GPIO Cntrl Register
|
||||||
|
* @param out -GPIO bitmap
|
||||||
|
* @param out -GPIO enable bitmap
|
||||||
|
*/
|
||||||
|
static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
|
||||||
|
{
|
||||||
|
u8 value;
|
||||||
|
device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
|
||||||
|
|
||||||
|
value = pci_read_config8(sm_dev, reg);
|
||||||
|
value &= ~(enable);
|
||||||
|
value |= out;
|
||||||
|
value &= ~(enable << 4);
|
||||||
|
pci_write_config8(sm_dev, reg, value);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------
|
||||||
|
*
|
||||||
|
* SPD address table - porting required
|
||||||
|
*/
|
||||||
|
static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm
|
||||||
|
/* socket 0 */
|
||||||
|
{
|
||||||
|
{0xAE, 0xAC},
|
||||||
|
{0xAA, 0xA8},
|
||||||
|
{0xA6, 0xA4},
|
||||||
|
{0xA2, 0xA0},
|
||||||
|
},
|
||||||
|
/* socket 1 */
|
||||||
|
{
|
||||||
|
{0xAE, 0xAC},
|
||||||
|
{0xAA, 0xA8},
|
||||||
|
{0xA6, 0xA4},
|
||||||
|
{0xA2, 0xA0},
|
||||||
|
},
|
||||||
|
/* socket 2 */
|
||||||
|
{
|
||||||
|
{0xAE, 0xAC},
|
||||||
|
{0xAA, 0xA8},
|
||||||
|
{0xA6, 0xA4},
|
||||||
|
{0xA2, 0xA0},
|
||||||
|
},
|
||||||
|
/* socket 3 */
|
||||||
|
{
|
||||||
|
{0xAE, 0xAC},
|
||||||
|
{0xAA, 0xA8},
|
||||||
|
{0xA6, 0xA4},
|
||||||
|
{0xA2, 0xA0},
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------
|
||||||
|
*
|
||||||
|
* readSmbusByteData - read a single SPD byte from any offset
|
||||||
|
*/
|
||||||
|
|
||||||
|
static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
|
||||||
|
{
|
||||||
|
unsigned int status;
|
||||||
|
UINT64 limit;
|
||||||
|
|
||||||
|
address |= 1; // set read bit
|
||||||
|
|
||||||
|
outb(0xFF, iobase + 0); // clear error status
|
||||||
|
outb(0x1F, iobase + 1); // clear error status
|
||||||
|
outb(offset, iobase + 3); // offset in eeprom
|
||||||
|
outb(address, iobase + 4); // slave address and read bit
|
||||||
|
outb(0x48, iobase + 2); // read byte command
|
||||||
|
|
||||||
|
// time limit to avoid hanging for unexpected error status (should never happen)
|
||||||
|
limit = __rdtsc () + 2000000000 / 10;
|
||||||
|
for (;;)
|
||||||
|
{
|
||||||
|
status = inb(iobase);
|
||||||
|
if (__rdtsc () > limit) break;
|
||||||
|
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
|
||||||
|
if ((status & 1) == 1) continue; // HostBusy set, keep waiting
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
buffer [0] = inb(iobase + 5);
|
||||||
|
if (status == 2) status = 0; // check for done with no errors
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------
|
||||||
|
*
|
||||||
|
* readSmbusByte - read a single SPD byte from the default offset
|
||||||
|
* this function is faster function readSmbusByteData
|
||||||
|
*/
|
||||||
|
|
||||||
|
static int readSmbusByte (int iobase, int address, char *buffer)
|
||||||
|
{
|
||||||
|
unsigned int status;
|
||||||
|
UINT64 limit;
|
||||||
|
|
||||||
|
outb(0xFF, iobase + 0); // clear error status
|
||||||
|
outb(0x44, iobase + 2); // read command
|
||||||
|
|
||||||
|
// time limit to avoid hanging for unexpected error status
|
||||||
|
limit = __rdtsc () + 2000000000 / 10;
|
||||||
|
for (;;)
|
||||||
|
{
|
||||||
|
status = inb(iobase);
|
||||||
|
if (__rdtsc () > limit) break;
|
||||||
|
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
|
||||||
|
if ((status & 1) == 1) continue; // HostBusy set, keep waiting
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
buffer [0] = inb(iobase + 5);
|
||||||
|
if (status == 2) status = 0; // check for done with no errors
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------
|
||||||
|
*
|
||||||
|
* readspd - Read one or more SPD bytes from a DIMM.
|
||||||
|
* Start with offset zero and read sequentially.
|
||||||
|
* Optimization relies on autoincrement to avoid
|
||||||
|
* sending offset for every byte.
|
||||||
|
* Reads 128 bytes in 7-8 ms at 400 KHz.
|
||||||
|
*/
|
||||||
|
|
||||||
|
static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
|
||||||
|
{
|
||||||
|
int index, error;
|
||||||
|
|
||||||
|
/* read the first byte using offset zero */
|
||||||
|
error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
|
||||||
|
if (error) {
|
||||||
|
return error;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* read the remaining bytes using auto-increment for speed */
|
||||||
|
for (index = 1; index < count; index++)
|
||||||
|
{
|
||||||
|
error = readSmbusByte (iobase, SmbusSlaveAddress, buffer + index);
|
||||||
|
if (error)
|
||||||
|
return error;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void writePmReg (int reg, int data)
|
||||||
|
{
|
||||||
|
outb(reg, 0xCD6);
|
||||||
|
outb(data, 0xCD7);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void setupFch (int ioBase)
|
||||||
|
{
|
||||||
|
writePmReg (0x2D, ioBase >> 8);
|
||||||
|
writePmReg (0x2C, ioBase | 1);
|
||||||
|
writePmReg (0x29, 0x80);
|
||||||
|
writePmReg (0x28, 0x61);
|
||||||
|
outb(66000000 / 400000 / 4, ioBase + 0x0E); // set SMBus clock to 400 KHz
|
||||||
|
}
|
||||||
|
|
||||||
|
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
|
||||||
|
{
|
||||||
|
int spdAddress, ioBase;
|
||||||
|
u8 i2c_channel;
|
||||||
|
device_t sm_dev;
|
||||||
|
|
||||||
|
if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
|
||||||
|
if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
|
||||||
|
if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
|
||||||
|
i2c_channel = (UINT8) info->SocketId;
|
||||||
|
|
||||||
|
/* set ght i2c channel
|
||||||
|
* GPIO54,53 control the HC4052 S1,S0
|
||||||
|
* S1 S0 true table
|
||||||
|
* 0 0 channel 1 (Socket1)
|
||||||
|
* 0 1 channel 2 (Socket2)
|
||||||
|
* 1 0 channel 3 (Socket3)
|
||||||
|
* 1 1 channel 4 (Socket4)
|
||||||
|
*/
|
||||||
|
sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03);
|
||||||
|
|
||||||
|
spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
|
||||||
|
if (spdAddress == 0)
|
||||||
|
return AGESA_ERROR;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SMBus Base Address was set during southbridge early setup.
|
||||||
|
* e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000
|
||||||
|
*/
|
||||||
|
sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0);
|
||||||
|
ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0);
|
||||||
|
setupFch(ioBase);
|
||||||
|
|
||||||
|
return readspd(ioBase, spdAddress, (void *)info->Buffer, 256);
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,201 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ACPI - create the Fixed ACPI Description Tables (FADT)
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <arch/acpi.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include "southbridge/amd/sb700/sb700.h"
|
||||||
|
|
||||||
|
u16 pm_base = SB700_ACPI_IO_BASE;
|
||||||
|
/* pm_base should be set in sb acpi */
|
||||||
|
/* pm_base should be got from bar2 of sb700. Here I compact ACPI
|
||||||
|
* registers into 32 bytes limit.
|
||||||
|
* */
|
||||||
|
|
||||||
|
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||||
|
{
|
||||||
|
acpi_header_t *header = &(fadt->header);
|
||||||
|
|
||||||
|
pm_base &= 0xFFFF;
|
||||||
|
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
|
||||||
|
|
||||||
|
/* Prepare the header */
|
||||||
|
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
|
||||||
|
memcpy(header->signature, "FACP", 4);
|
||||||
|
header->length = 244;
|
||||||
|
header->revision = 3;
|
||||||
|
memcpy(header->oem_id, OEM_ID, 6);
|
||||||
|
memcpy(header->oem_table_id, "AMD ", 8);
|
||||||
|
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||||
|
header->asl_compiler_revision = 0;
|
||||||
|
|
||||||
|
fadt->firmware_ctrl = (u32) facs;
|
||||||
|
fadt->dsdt = (u32) dsdt;
|
||||||
|
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
|
||||||
|
fadt->preferred_pm_profile = 0x03;
|
||||||
|
fadt->sci_int = 9;
|
||||||
|
/* disable system management mode by setting to 0: */
|
||||||
|
fadt->smi_cmd = 0;
|
||||||
|
fadt->acpi_enable = 0xf0;
|
||||||
|
fadt->acpi_disable = 0xf1;
|
||||||
|
fadt->s4bios_req = 0x0;
|
||||||
|
fadt->pstate_cnt = 0xe2;
|
||||||
|
|
||||||
|
pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
|
||||||
|
pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
|
||||||
|
pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
|
||||||
|
pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
|
||||||
|
pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
|
||||||
|
pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
|
||||||
|
pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
|
||||||
|
pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
|
||||||
|
|
||||||
|
/* CpuControl is in \_PR.CPU0, 6 bytes */
|
||||||
|
pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF);
|
||||||
|
pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8);
|
||||||
|
|
||||||
|
pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
|
||||||
|
pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
|
||||||
|
|
||||||
|
pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
|
||||||
|
pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
|
||||||
|
|
||||||
|
pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
|
||||||
|
* the contents of the PM registers at
|
||||||
|
* index 60-6B to decode ACPI I/O address.
|
||||||
|
* AcpiSmiEn & SmiCmdEn*/
|
||||||
|
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
|
||||||
|
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
|
||||||
|
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
|
||||||
|
fadt->pm1b_evt_blk = 0x0000;
|
||||||
|
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
|
||||||
|
fadt->pm1b_cnt_blk = 0x0000;
|
||||||
|
fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
|
||||||
|
fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
|
||||||
|
fadt->gpe0_blk = ACPI_GPE0_BLK;
|
||||||
|
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
|
||||||
|
|
||||||
|
fadt->pm1_evt_len = 4;
|
||||||
|
fadt->pm1_cnt_len = 2;
|
||||||
|
fadt->pm2_cnt_len = 1;
|
||||||
|
fadt->pm_tmr_len = 4;
|
||||||
|
fadt->gpe0_blk_len = 8;
|
||||||
|
fadt->gpe1_blk_len = 0;
|
||||||
|
fadt->gpe1_base = 0;
|
||||||
|
|
||||||
|
fadt->cst_cnt = 0xe3;
|
||||||
|
fadt->p_lvl2_lat = 101;
|
||||||
|
fadt->p_lvl3_lat = 1001;
|
||||||
|
fadt->flush_size = 0;
|
||||||
|
fadt->flush_stride = 0;
|
||||||
|
fadt->duty_offset = 1;
|
||||||
|
fadt->duty_width = 3;
|
||||||
|
fadt->day_alrm = 0; /* 0x7d these have to be */
|
||||||
|
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
|
||||||
|
fadt->century = 0; /* 0x7f to make rtc alrm work */
|
||||||
|
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
|
||||||
|
fadt->flags = 0x0001c1a5;/* 0x25; */
|
||||||
|
|
||||||
|
fadt->res2 = 0;
|
||||||
|
|
||||||
|
fadt->reset_reg.space_id = 1;
|
||||||
|
fadt->reset_reg.bit_width = 8;
|
||||||
|
fadt->reset_reg.bit_offset = 0;
|
||||||
|
fadt->reset_reg.resv = 0;
|
||||||
|
fadt->reset_reg.addrl = 0xcf9;
|
||||||
|
fadt->reset_reg.addrh = 0x0;
|
||||||
|
|
||||||
|
fadt->reset_value = 6;
|
||||||
|
fadt->x_firmware_ctl_l = (u32) facs;
|
||||||
|
fadt->x_firmware_ctl_h = 0;
|
||||||
|
fadt->x_dsdt_l = (u32) dsdt;
|
||||||
|
fadt->x_dsdt_h = 0;
|
||||||
|
|
||||||
|
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||||
|
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||||
|
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||||
|
fadt->x_pm1a_evt_blk.resv = 0;
|
||||||
|
fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
|
||||||
|
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||||
|
|
||||||
|
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||||
|
fadt->x_pm1b_evt_blk.bit_width = 4;
|
||||||
|
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||||
|
fadt->x_pm1b_evt_blk.resv = 0;
|
||||||
|
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||||
|
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||||
|
|
||||||
|
|
||||||
|
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||||
|
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||||
|
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||||
|
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||||
|
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
|
||||||
|
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||||
|
|
||||||
|
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||||
|
fadt->x_pm1b_cnt_blk.bit_width = 2;
|
||||||
|
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||||
|
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||||
|
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||||
|
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||||
|
|
||||||
|
|
||||||
|
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||||
|
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||||
|
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||||
|
fadt->x_pm2_cnt_blk.resv = 0;
|
||||||
|
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
|
||||||
|
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||||
|
|
||||||
|
|
||||||
|
fadt->x_pm_tmr_blk.space_id = 1;
|
||||||
|
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||||
|
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||||
|
fadt->x_pm_tmr_blk.resv = 0;
|
||||||
|
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
|
||||||
|
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||||
|
|
||||||
|
|
||||||
|
fadt->x_gpe0_blk.space_id = 1;
|
||||||
|
fadt->x_gpe0_blk.bit_width = 32;
|
||||||
|
fadt->x_gpe0_blk.bit_offset = 0;
|
||||||
|
fadt->x_gpe0_blk.resv = 0;
|
||||||
|
fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
|
||||||
|
fadt->x_gpe0_blk.addrh = 0x0;
|
||||||
|
|
||||||
|
|
||||||
|
fadt->x_gpe1_blk.space_id = 1;
|
||||||
|
fadt->x_gpe1_blk.bit_width = 0;
|
||||||
|
fadt->x_gpe1_blk.bit_offset = 0;
|
||||||
|
fadt->x_gpe1_blk.resv = 0;
|
||||||
|
fadt->x_gpe1_blk.addrl = 0;
|
||||||
|
fadt->x_gpe1_blk.addrh = 0x0;
|
||||||
|
|
||||||
|
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,154 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <cpu/amd/amdfam10_sysconf.h>
|
||||||
|
#include "agesawrapper.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||||
|
* and acpi_tables busnum is default.
|
||||||
|
*/
|
||||||
|
u8 bus_isa;
|
||||||
|
u8 bus_sp5100[2];
|
||||||
|
u8 bus_sr5650[14];
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||||
|
* You may need to preset pci1234 for HTIO board,
|
||||||
|
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||||
|
*/
|
||||||
|
u32 pci1234x[] = {
|
||||||
|
0x0000ff0,
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* HT Chain device num, actually it is unit id base of every ht device in chain,
|
||||||
|
* assume every chain only have 4 ht device at most
|
||||||
|
*/
|
||||||
|
u32 hcdnx[] = {
|
||||||
|
0x20202020,
|
||||||
|
};
|
||||||
|
|
||||||
|
u32 bus_type[256];
|
||||||
|
|
||||||
|
u32 sbdn_sr5650;
|
||||||
|
u32 sbdn_sp5100;
|
||||||
|
|
||||||
|
static u32 get_bus_conf_done = 0;
|
||||||
|
|
||||||
|
|
||||||
|
void get_bus_conf(void)
|
||||||
|
{
|
||||||
|
u32 status;
|
||||||
|
|
||||||
|
device_t dev;
|
||||||
|
int i, j;
|
||||||
|
|
||||||
|
if (get_bus_conf_done == 1)
|
||||||
|
return; /* do it only once */
|
||||||
|
|
||||||
|
get_bus_conf_done = 1;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This is the call to AmdInitLate. It is really in the wrong place, conceptually,
|
||||||
|
* but functionally within the coreboot model, this is the best place to make the
|
||||||
|
* call. The logically correct place to call AmdInitLate is after PCI scan is done,
|
||||||
|
* after the decision about S3 resume is made, and before the system tables are
|
||||||
|
* written into RAM. The routine that is responsible for writing the tables is
|
||||||
|
* "write_tables", called near the end of "hardwaremain". There is no platform
|
||||||
|
* specific entry point between the S3 resume decision point and the call to
|
||||||
|
* "write_tables", and the next platform specific entry points are the calls to
|
||||||
|
* the ACPI table write functions. The first of ose would seem to be the right
|
||||||
|
* place, but other table write functions, e.g. the PIRQ table write function, are
|
||||||
|
* called before the ACPI tables are written. This routine is called at the beginning
|
||||||
|
* of each of the write functions called prior to the ACPI write functions, so this
|
||||||
|
* becomes the best place for this call.
|
||||||
|
*/
|
||||||
|
status = agesawrapper_amdinitlate();
|
||||||
|
if(status) {
|
||||||
|
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
|
||||||
|
}
|
||||||
|
|
||||||
|
sbdn_sp5100 = 0;
|
||||||
|
|
||||||
|
for (i = 0; i < 0; i++) {
|
||||||
|
bus_sp5100[i] = 0;
|
||||||
|
}
|
||||||
|
for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
|
||||||
|
bus_sr5650[i] = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < 256; i++) {
|
||||||
|
bus_type[i] = 0; /* default ISA bus. */
|
||||||
|
}
|
||||||
|
|
||||||
|
bus_type[0] = 1; /* pci */
|
||||||
|
|
||||||
|
bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff;
|
||||||
|
// bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||||
|
bus_sp5100[0] = bus_sr5650[0];
|
||||||
|
|
||||||
|
/* sp5100 */
|
||||||
|
dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
|
||||||
|
|
||||||
|
if (dev) {
|
||||||
|
bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_isa++;
|
||||||
|
for (j = bus_sp5100[1]; j < bus_isa; j++)
|
||||||
|
bus_type[j] = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* sr5650 */
|
||||||
|
for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
|
||||||
|
dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0));
|
||||||
|
if (dev) {
|
||||||
|
bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
if(255 != bus_sr5650[i]) {
|
||||||
|
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_isa++;
|
||||||
|
bus_type[bus_sr5650[i]] = 1; /* PCI bus. */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
for (i = 0; i < 4; i++) {
|
||||||
|
dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i));
|
||||||
|
if (dev) {
|
||||||
|
bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_isa++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
for (j = bus_sp5100[2]; j < bus_isa; j++)
|
||||||
|
bus_type[j] = 1;
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* I/O APICs: APIC ID Version State Address */
|
||||||
|
bus_isa = 10;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,122 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <arch/pirq_routing.h>
|
||||||
|
#include <cpu/amd/amdfam10_sysconf.h>
|
||||||
|
|
||||||
|
|
||||||
|
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||||
|
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||||
|
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||||
|
u8 slot, u8 rfu)
|
||||||
|
{
|
||||||
|
pirq_info->bus = bus;
|
||||||
|
pirq_info->devfn = devfn;
|
||||||
|
pirq_info->irq[0].link = link0;
|
||||||
|
pirq_info->irq[0].bitmap = bitmap0;
|
||||||
|
pirq_info->irq[1].link = link1;
|
||||||
|
pirq_info->irq[1].bitmap = bitmap1;
|
||||||
|
pirq_info->irq[2].link = link2;
|
||||||
|
pirq_info->irq[2].bitmap = bitmap2;
|
||||||
|
pirq_info->irq[3].link = link3;
|
||||||
|
pirq_info->irq[3].bitmap = bitmap3;
|
||||||
|
pirq_info->slot = slot;
|
||||||
|
pirq_info->rfu = rfu;
|
||||||
|
}
|
||||||
|
extern u8 bus_isa;
|
||||||
|
extern u8 bus_sp5100[2];
|
||||||
|
extern unsigned long sbdn_sp5100;
|
||||||
|
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
|
||||||
|
struct irq_routing_table *pirq;
|
||||||
|
struct irq_info *pirq_info;
|
||||||
|
u32 slot_num;
|
||||||
|
u8 *v;
|
||||||
|
|
||||||
|
u8 sum = 0;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
|
||||||
|
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
|
||||||
|
|
||||||
|
|
||||||
|
/* Align the table to be 16 byte aligned. */
|
||||||
|
addr += 15;
|
||||||
|
addr &= ~15;
|
||||||
|
|
||||||
|
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||||
|
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||||
|
|
||||||
|
pirq = (void *)(addr);
|
||||||
|
v = (u8 *) (addr);
|
||||||
|
|
||||||
|
pirq->signature = PIRQ_SIGNATURE;
|
||||||
|
pirq->version = PIRQ_VERSION;
|
||||||
|
|
||||||
|
pirq->rtr_bus = bus_sp5100[0];
|
||||||
|
pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4;
|
||||||
|
|
||||||
|
pirq->exclusive_irqs = 0;
|
||||||
|
|
||||||
|
pirq->rtr_vendor = 0x1002;
|
||||||
|
pirq->rtr_device = 0x4384;
|
||||||
|
|
||||||
|
pirq->miniport_data = 0;
|
||||||
|
|
||||||
|
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||||
|
|
||||||
|
pirq_info = (void *)(&pirq->checksum + 1);
|
||||||
|
slot_num = 0;
|
||||||
|
|
||||||
|
|
||||||
|
/* pci bridge */
|
||||||
|
write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4,
|
||||||
|
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||||
|
0);
|
||||||
|
pirq_info++;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
slot_num++;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
pirq->size = 32 + 16 * slot_num;
|
||||||
|
|
||||||
|
for (i = 0; i < pirq->size; i++)
|
||||||
|
sum += v[i];
|
||||||
|
|
||||||
|
sum = pirq->checksum - sum;
|
||||||
|
|
||||||
|
if (sum != pirq->checksum) {
|
||||||
|
pirq->checksum = sum;
|
||||||
|
}
|
||||||
|
|
||||||
|
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||||
|
|
||||||
|
return (unsigned long)pirq_info;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,73 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <boot/tables.h>
|
||||||
|
#include <cpu/x86/msr.h>
|
||||||
|
#include <cpu/amd/mtrr.h>
|
||||||
|
#include <device/pci_def.h>
|
||||||
|
#include "southbridge/amd/sr5650/cmn.h"
|
||||||
|
#include "chip.h"
|
||||||
|
|
||||||
|
void set_pcie_dereset(void);
|
||||||
|
void set_pcie_reset(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void set_pcie_reset(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Release Resets to PCIe Links
|
||||||
|
* PCIE_RESET_GPIO1,2,4,5
|
||||||
|
*/
|
||||||
|
void set_pcie_dereset(void)
|
||||||
|
{
|
||||||
|
device_t pcie_core_dev;
|
||||||
|
|
||||||
|
pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
|
||||||
|
set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707);
|
||||||
|
set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*************************************************
|
||||||
|
* enable the dedicated function in h8qgi board.
|
||||||
|
*************************************************/
|
||||||
|
static void h8qgi_enable(device_t dev)
|
||||||
|
{
|
||||||
|
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
|
||||||
|
int add_mainboard_resources(struct lb_memory *mem)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
struct chip_operations mainboard_ops = {
|
||||||
|
CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
|
||||||
|
.enable_dev = h8qgi_enable,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,200 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <arch/smp/mpspec.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <arch/cpu.h>
|
||||||
|
#include <cpu/x86/lapic.h>
|
||||||
|
#include <cpu/amd/amdfam10_sysconf.h>
|
||||||
|
|
||||||
|
extern u8 bus_sr5650[14];
|
||||||
|
extern u8 bus_sp5100[2];
|
||||||
|
extern u32 bus_type[256];
|
||||||
|
extern u32 sbdn_sr5650;
|
||||||
|
extern u32 sbdn_sp5100;
|
||||||
|
|
||||||
|
|
||||||
|
static void *smp_write_config_table(void *v)
|
||||||
|
{
|
||||||
|
struct mp_config_table *mc;
|
||||||
|
int bus_isa;
|
||||||
|
u32 apicid_sp5100;
|
||||||
|
u32 apicid_sr5650;
|
||||||
|
device_t dev;
|
||||||
|
u32 dword;
|
||||||
|
u8 byte;
|
||||||
|
|
||||||
|
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||||
|
mptable_init(mc, LAPIC_ADDR);
|
||||||
|
|
||||||
|
smp_write_processors(mc);
|
||||||
|
get_bus_conf();
|
||||||
|
mptable_write_buses(mc, NULL, &bus_isa);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AGESA v5 Apply apic enumeration rules
|
||||||
|
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
|
||||||
|
* put the local-APICs at m..z
|
||||||
|
* For systems with < 16 APICs, put the Local-APICs at 0..n and
|
||||||
|
* put the IO-APICs at (n + 1)..z
|
||||||
|
*/
|
||||||
|
#if CONFIG_MAX_CPUS >= 16
|
||||||
|
apicid_sp5100 = 0x0;
|
||||||
|
#else
|
||||||
|
apicid_sp5100 = CONFIG_MAX_CPUS + 1
|
||||||
|
#endif
|
||||||
|
apicid_sr5650 = apicid_sp5100 + 1;
|
||||||
|
|
||||||
|
//bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
|
||||||
|
dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
|
||||||
|
if (dev) {
|
||||||
|
/* Set SP5100 IOAPIC ID */
|
||||||
|
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
|
||||||
|
smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
|
||||||
|
|
||||||
|
/* Initialize interrupt mapping */
|
||||||
|
/* aza */
|
||||||
|
byte = pci_read_config8(dev, 0x63);
|
||||||
|
byte &= 0xf8;
|
||||||
|
byte |= 0; /* 0: INTA, ...., 7: INTH */
|
||||||
|
pci_write_config8(dev, 0x63, byte);
|
||||||
|
/* SATA */
|
||||||
|
dword = pci_read_config32(dev, 0xAC);
|
||||||
|
dword &= ~(7 << 26);
|
||||||
|
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
|
||||||
|
/* dword |= 1<<22; PIC and APIC co exists */
|
||||||
|
pci_write_config32(dev, 0xAC, dword);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 00:12.0: PROG SATA : INT F
|
||||||
|
* 00:13.0: INTA USB_0
|
||||||
|
* 00:13.1: INTB USB_1
|
||||||
|
* 00:13.2: INTC USB_2
|
||||||
|
* 00:13.3: INTD USB_3
|
||||||
|
* 00:13.4: INTC USB_4
|
||||||
|
* 00:13.5: INTD USB2
|
||||||
|
* 00:14.1: INTA IDE
|
||||||
|
* 00:14.2: Prog HDA : INT E
|
||||||
|
* 00:14.5: INTB ACI
|
||||||
|
* 00:14.6: INTB MCI
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Set RS5650 IOAPIC ID */
|
||||||
|
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
|
||||||
|
if (dev) {
|
||||||
|
pci_write_config32(dev, 0xF8, 0x1);
|
||||||
|
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
|
||||||
|
smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||||
|
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||||
|
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||||
|
|
||||||
|
mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
|
||||||
|
|
||||||
|
/* PCI interrupts are level triggered, and are
|
||||||
|
* associated with a specific bus/device/function tuple.
|
||||||
|
*/
|
||||||
|
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin))
|
||||||
|
|
||||||
|
/* SMBUS */
|
||||||
|
//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
|
||||||
|
|
||||||
|
/* HD Audio */
|
||||||
|
PCI_INT(0x0, 0x14, 0x2, 0x10);
|
||||||
|
|
||||||
|
/* USB */
|
||||||
|
/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
|
||||||
|
/* EHCI hard-wired to 02h, corresponding to using INTB# */
|
||||||
|
/* USB1 */
|
||||||
|
PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
|
||||||
|
PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
|
||||||
|
PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
|
||||||
|
|
||||||
|
/* USB2 */
|
||||||
|
PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
|
||||||
|
PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
|
||||||
|
PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
|
||||||
|
|
||||||
|
/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
|
||||||
|
PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
|
||||||
|
|
||||||
|
/* SATA */
|
||||||
|
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
|
||||||
|
|
||||||
|
/* on board NIC & Slot PCIE. */
|
||||||
|
/* configuration B doesnt need dev 5,6,7 */
|
||||||
|
/*
|
||||||
|
* PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
|
||||||
|
* PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
|
||||||
|
* PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
|
||||||
|
*/
|
||||||
|
|
||||||
|
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
|
||||||
|
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
|
||||||
|
|
||||||
|
/* PCI slots */
|
||||||
|
/* PCI_SLOT 0. */
|
||||||
|
PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
|
||||||
|
PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
|
||||||
|
PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
|
||||||
|
PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
|
||||||
|
|
||||||
|
/* PCI_SLOT 1. */
|
||||||
|
PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
|
||||||
|
PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
|
||||||
|
PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
|
||||||
|
PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
|
||||||
|
|
||||||
|
/* PCI_SLOT 2. */
|
||||||
|
PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
|
||||||
|
PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
|
||||||
|
PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
|
||||||
|
PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
|
||||||
|
|
||||||
|
|
||||||
|
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||||
|
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||||
|
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||||
|
/* There is no extension information... */
|
||||||
|
|
||||||
|
/* Compute the checksums */
|
||||||
|
mc->mpe_checksum =
|
||||||
|
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||||
|
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||||
|
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
|
||||||
|
mc, smp_next_mpe_entry(mc));
|
||||||
|
return smp_next_mpe_entry(mc);
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long write_smp_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
void *v;
|
||||||
|
v = smp_write_floating_table(addr);
|
||||||
|
return (unsigned long)smp_write_config_table(v);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "AGESA.h"
|
||||||
|
#include "amdlib.h"
|
||||||
|
#include "Ids.h"
|
||||||
|
#include "heapManager.h"
|
||||||
|
#include "platform_oem.h"
|
||||||
|
#include "Filecode.h"
|
||||||
|
|
||||||
|
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------*/
|
||||||
|
/**
|
||||||
|
* OemCustomizeInitEarly
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* This is the stub function will call the host environment through the binary block
|
||||||
|
* interface (call-out port) to provide a user hook opportunity
|
||||||
|
*
|
||||||
|
* Parameters:
|
||||||
|
* @param[in] **PeiServices
|
||||||
|
* @param[in] *InitEarly
|
||||||
|
*
|
||||||
|
* @retval VOID
|
||||||
|
*
|
||||||
|
**/
|
||||||
|
/*---------------------------------------------------------------------------------------*/
|
||||||
|
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
|
||||||
|
{
|
||||||
|
//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,29 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _PLATFORM_OEM_H_
|
||||||
|
#define _PLATFORM_OEM_H_
|
||||||
|
|
||||||
|
#include "Porting.h"
|
||||||
|
#include "AGESA.h"
|
||||||
|
#include "amdlib.h"
|
||||||
|
|
||||||
|
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
|
||||||
|
|
||||||
|
#endif //_PLATFORM_OEM_H_
|
||||||
|
|
@ -0,0 +1,132 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <lib.h>
|
||||||
|
#include <reset.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <arch/romcc_io.h>
|
||||||
|
#include <arch/cpu.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <arch/stages.h>
|
||||||
|
#include "cpu/x86/bist.h"
|
||||||
|
#include "cpu/x86/lapic/boot_cpu.c"
|
||||||
|
#include "agesawrapper.h"
|
||||||
|
#include "northbridge/amd/agesa/family10/reset_test.h"
|
||||||
|
#include "southbridge/amd/sr5650/sr5650.h"
|
||||||
|
#include "southbridge/amd/sb700/sb700.h"
|
||||||
|
#include "superio/nuvoton/wpcm450/wpcm450.h"
|
||||||
|
|
||||||
|
extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
|
||||||
|
|
||||||
|
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
agesawrapper_amdinitmmio();
|
||||||
|
if (!cpu_init_detectedx && boot_cpu()) {
|
||||||
|
post_code(0x30);
|
||||||
|
/* SR56x0 pcie bridges block pci_locate_device() before pcie training.
|
||||||
|
* disable all pcie bridges on SR56x0 to work around it
|
||||||
|
*/
|
||||||
|
sr5650_disable_pcie_bridge();
|
||||||
|
post_code(0x31);
|
||||||
|
sb7xx_51xx_lpc_port80();
|
||||||
|
post_code(0x32);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Halt if there was a built in self test failure */
|
||||||
|
post_code(0x33);
|
||||||
|
report_bist_failure(bist);
|
||||||
|
|
||||||
|
enable_sr5650_dev8();
|
||||||
|
sb7xx_51xx_lpc_init();
|
||||||
|
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
|
||||||
|
wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
|
||||||
|
sb7xx_51xx_disable_wideio(0);
|
||||||
|
post_code(0x34);
|
||||||
|
|
||||||
|
uart_init();
|
||||||
|
post_code(0x35);
|
||||||
|
console_init();
|
||||||
|
|
||||||
|
val = cpuid_eax(1);
|
||||||
|
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
|
||||||
|
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
|
||||||
|
|
||||||
|
post_code(0x37);
|
||||||
|
val = agesawrapper_amdinitreset();
|
||||||
|
if (val) {
|
||||||
|
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
|
||||||
|
} else {
|
||||||
|
printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
post_code(0x38);
|
||||||
|
val = agesawrapper_amdinitearly();
|
||||||
|
if(val) {
|
||||||
|
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
|
||||||
|
} else {
|
||||||
|
printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
sr5650_early_setup();
|
||||||
|
post_code(0x39);
|
||||||
|
|
||||||
|
sb7xx_51xx_early_setup();
|
||||||
|
sr5650_htinit();
|
||||||
|
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||||
|
if (!warm_reset_detect(0)) {
|
||||||
|
print_info("...WARM RESET...\n\n\n");
|
||||||
|
distinguish_cpu_resets(0);
|
||||||
|
soft_reset();
|
||||||
|
die("After soft_reset_x - shouldn't see this message!!!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
post_code(0x40);
|
||||||
|
val = agesawrapper_amdinitpost();
|
||||||
|
if (val) {
|
||||||
|
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
|
||||||
|
}
|
||||||
|
printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
|
||||||
|
|
||||||
|
post_code(0x41);
|
||||||
|
val = agesawrapper_amdinitenv();
|
||||||
|
if(val) {
|
||||||
|
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
|
||||||
|
}
|
||||||
|
printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
|
||||||
|
|
||||||
|
post_code(0x42);
|
||||||
|
sr5650_before_pci_init();
|
||||||
|
sb7xx_51xx_before_pci_init();
|
||||||
|
|
||||||
|
post_code(0x50);
|
||||||
|
print_debug("Disabling cache as ram ");
|
||||||
|
disable_cache_as_ram();
|
||||||
|
print_debug("done\n");
|
||||||
|
|
||||||
|
post_code(0x51);
|
||||||
|
copy_and_run(0);
|
||||||
|
|
||||||
|
/* We will not return, Should never see this message and post code. */
|
||||||
|
print_debug("should not be here -\n");
|
||||||
|
post_code(0x54);
|
||||||
|
}
|
||||||
|
|
||||||
Loading…
Reference in New Issue