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iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned 

The PCI registers should be accessed aligned and 0x62 is not 32bit
aligned therefore this patch changes it to a 16bit access.

Change-Id: I00725a4569f471eedb061834f626911b42e734fb
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1631
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
This commit is contained in:
Sebastian Andrzej Siewior 2012-10-26 19:02:44 +02:00 committed by Stefan Reinauer
parent 3e9155dddf
commit 95c607fead
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/iwave/iWRainbowG6/romstage.c
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@ -321,11 +321,11 @@ static void poulsbo_setup_Stage1Regs(void)
static void poulsbo_setup_Stage2Regs(void) static void poulsbo_setup_Stage2Regs(void)
{ {
u32 reg32; u16 reg16;
printk(BIOS_DEBUG, "Reserved"); printk(BIOS_DEBUG, "Reserved");
reg32 = pci_read_config32(PCI_DEV(0, 0x2, 0), 0x62); reg16 = pci_read_config16(PCI_DEV(0, 0x2, 0), 0x62);
pci_write_config32(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3)); pci_write_config16(PCI_DEV(0, 0x2, 0), 0x62, (reg16 | 0x3));
/* Slot capabilities */ /* Slot capabilities */
pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500); pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500);
pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500); pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);