nb/intel/nehalem: Rename to ironlake

The code is for Arrandale CPUs, whose System Agent is Ironlake.

This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.

Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.

Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/Makefile.inc

@@ -10,7 +10,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1

src/cpu/intel/model_2065x/acpi.c

@@ -216,7 +216,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 		/* Max Non-Turbo Ratio */
 		ratio_max = (msr.lo >> 8) & 0xff;
 	}
-	clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3;
+	clock_max = ratio_max * IRONLAKE_BCLK + ratio_max / 3;
 
 	/* Calculate CPU TDP in mW */
 	power_max = 25000;
@@ -277,7 +277,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 
 		/* Calculate power at this ratio */
 		power = calculate_power(power_max, ratio_max, ratio);
-		clock = ratio * NEHALEM_BCLK + ratio / 3;
+		clock = ratio * IRONLAKE_BCLK + ratio / 3;
 
 		acpigen_write_PSS_package(
 			clock,			/*MHz*/

src/cpu/intel/model_2065x/model_2065x.h

@@ -16,7 +16,7 @@
 #define _CPU_INTEL_MODEL_2065X_H
 
 /* Nehalem bus clock is fixed at 133MHz */
-#define NEHALEM_BCLK		133
+#define IRONLAKE_BCLK		133
 
 #define MSR_CORE_THREAD_COUNT		0x35
 #define MSR_FEATURE_CONFIG		0x13c

src/cpu/intel/model_2065x/model_2065x_init.c

@@ -197,7 +197,7 @@ static void set_max_ratio(void)
 	wrmsr(IA32_PERF_CTL, perf_ctl);
 
 	printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
-	       ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK);
+	       ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK);
 }
 
 static void set_energy_perf_bias(u8 policy)

src/cpu/x86/Kconfig

@@ -140,7 +140,7 @@ config SMM_LAPIC_REMAP_MITIGATION
 	bool
 	default y if NORTHBRIDGE_INTEL_I945
 	default y if NORTHBRIDGE_INTEL_GM45
-	default y if NORTHBRIDGE_INTEL_NEHALEM
+	default y if NORTHBRIDGE_INTEL_IRONLAKE
 	default n
 
 config SERIALIZED_SMM_INITIALIZATION

src/drivers/intel/gma/Kconfig

@@ -66,7 +66,7 @@ config GFX_GMA_ANALOG_I2C_HDMI_D
 config GFX_GMA
 	def_bool y
 	depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \
-		|| NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \
+		|| NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \
 		|| NORTHBRIDGE_INTEL_HASWELL \
 		|| SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \
 		|| SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \
@@ -83,7 +83,7 @@ config GFX_GMA_PANEL_1_ON_EDP
 config GFX_GMA_PANEL_1_ON_LVDS
 	bool
 	depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT
-	default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM
+	default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE
 	default n
 
 if GFX_GMA
@@ -99,7 +99,7 @@ config GFX_GMA_GENERATION
 	default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \
 				SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
 	default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL
-	default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE
+	default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE
 	default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X
 
 config GFX_GMA_PANEL_1_PORT

src/mainboard/lenovo/t410/Kconfig

@@ -3,7 +3,7 @@ if BOARD_LENOVO_T410
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select SYSTEM_TYPE_LAPTOP
-	select NORTHBRIDGE_INTEL_NEHALEM
+	select NORTHBRIDGE_INTEL_IRONLAKE
 	select SOUTHBRIDGE_INTEL_IBEXPEAK
 	select EC_LENOVO_PMH7
 	select EC_LENOVO_H8

src/mainboard/lenovo/t410/devicetree.cb

@@ -15,7 +15,7 @@
 ## GNU General Public License for more details.
 ##
 
-chip northbridge/intel/nehalem
+chip northbridge/intel/ironlake
 	# IGD Displays
 	register "gfx.ndid" = "3"
 	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"

src/mainboard/lenovo/t410/dsdt.asl

@@ -45,7 +45,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <northbridge/intel/nehalem/acpi/nehalem.asl>
+			#include <northbridge/intel/ironlake/acpi/ironlake.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>

src/mainboard/lenovo/t410/romstage.c

@@ -20,7 +20,7 @@
 #include <device/pci_ops.h>
 #include <southbridge/intel/ibexpeak/pch.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	/* Enabled, Current table lookup index, OC map */

src/mainboard/lenovo/t410/smihandler.c

@@ -19,7 +19,7 @@
 #include <cpu/x86/smm.h>
 #include <southbridge/intel/ibexpeak/nvs.h>
 #include <southbridge/intel/common/pmutil.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include <ec/acpi/ec.h>
 #include <ec/lenovo/h8/h8.h>
 #include <delay.h>

src/mainboard/lenovo/x201/Kconfig

@@ -3,7 +3,7 @@ if BOARD_LENOVO_X201
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select SYSTEM_TYPE_LAPTOP
-	select NORTHBRIDGE_INTEL_NEHALEM
+	select NORTHBRIDGE_INTEL_IRONLAKE
 	select SOUTHBRIDGE_INTEL_IBEXPEAK
 	select EC_LENOVO_PMH7
 	select EC_LENOVO_H8

src/mainboard/lenovo/x201/devicetree.cb

@@ -15,7 +15,7 @@
 ## GNU General Public License for more details.
 ##
 
-chip northbridge/intel/nehalem
+chip northbridge/intel/ironlake
 	# IGD Displays
 	register "gfx.ndid" = "3"
 	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"

src/mainboard/lenovo/x201/dsdt.asl

@@ -45,7 +45,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <northbridge/intel/nehalem/acpi/nehalem.asl>
+			#include <northbridge/intel/ironlake/acpi/ironlake.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>

src/mainboard/lenovo/x201/mainboard.c

@@ -18,7 +18,7 @@
 
 #include <device/device.h>
 #include <ec/acpi/ec.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include "dock.h"
 #include <drivers/intel/gma/int15.h>

src/mainboard/lenovo/x201/romstage.c

@@ -21,7 +21,7 @@
 #include <ec/acpi/ec.h>
 
 #include <southbridge/intel/ibexpeak/pch.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	/* Enabled, Current table lookup index, OC map */

src/mainboard/lenovo/x201/smihandler.c

@@ -19,7 +19,7 @@
 #include <cpu/x86/smm.h>
 #include <southbridge/intel/ibexpeak/nvs.h>
 #include <southbridge/intel/common/pmutil.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include <ec/acpi/ec.h>
 #include <ec/lenovo/h8/h8.h>
 #include <delay.h>

src/mainboard/packardbell/ms2290/Kconfig

@@ -3,7 +3,7 @@ if BOARD_PACKARDBELL_MS2290
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select SYSTEM_TYPE_LAPTOP
-	select NORTHBRIDGE_INTEL_NEHALEM
+	select NORTHBRIDGE_INTEL_IRONLAKE
 	select SOUTHBRIDGE_INTEL_IBEXPEAK
 	select HAVE_OPTION_TABLE
 	select HAVE_CMOS_DEFAULT

src/mainboard/packardbell/ms2290/devicetree.cb

@@ -15,7 +15,7 @@
 ## GNU General Public License for more details.
 ##
 
-chip northbridge/intel/nehalem
+chip northbridge/intel/ironlake
 	# IGD Displays
 	register "gfx.ndid" = "3"
 	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"

src/mainboard/packardbell/ms2290/dsdt.asl

@@ -39,7 +39,7 @@ DefinitionBlock(
 	Scope (\_SB) {
 		Device (PCI0)
 		{
-			#include <northbridge/intel/nehalem/acpi/nehalem.asl>
+			#include <northbridge/intel/ironlake/acpi/ironlake.asl>
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>

src/mainboard/packardbell/ms2290/mainboard.c

@@ -18,7 +18,7 @@
 
 #include <device/device.h>
 #include <arch/io.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/acpi/ec.h>
 #include <drivers/intel/gma/int15.h>

src/mainboard/packardbell/ms2290/romstage.c

@@ -19,7 +19,7 @@
 #include <stdint.h>
 
 #include <southbridge/intel/ibexpeak/pch.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 
 /* Seems copied from Lenovo Thinkpad x201, might be wrong */
 const struct southbridge_usb_port mainboard_usb_ports[] = {

src/mainboard/packardbell/ms2290/smihandler.c

@@ -19,7 +19,7 @@
 #include <device/pci_ops.h>
 #include <southbridge/intel/ibexpeak/nvs.h>
 #include <southbridge/intel/common/pmutil.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include <ec/acpi/ec.h>
 
 void mainboard_smi_gpi(u32 gpi_sts)

src/northbridge/intel/ironlake/Kconfig

@@ -13,7 +13,7 @@
 ## GNU General Public License for more details.
 ##
 
-config NORTHBRIDGE_INTEL_NEHALEM
+config NORTHBRIDGE_INTEL_IRONLAKE
 	bool
 	select CPU_INTEL_MODEL_2065X
 	select VGA
@@ -22,7 +22,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
 	select CACHE_MRC_SETTINGS
 	select HAVE_DEBUG_RAM_SETUP
 
-if NORTHBRIDGE_INTEL_NEHALEM
+if NORTHBRIDGE_INTEL_IRONLAKE
 
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY

src/northbridge/intel/ironlake/Makefile.inc

@@ -13,7 +13,7 @@
 # GNU General Public License for more details.
 #
 
-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y)
+ifeq ($(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE),y)
 
 bootblock-y += bootblock.c
 

src/northbridge/intel/ironlake/acpi.c

@@ -21,7 +21,7 @@
 #include <types.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include "nehalem.h"
+#include "ironlake.h"
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {

src/northbridge/intel/ironlake/acpi/ironlake.asl

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include "../nehalem.h"
+#include "../ironlake.h"
 #include "hostbridge.asl"
 #include <southbridge/intel/common/rcba.h>
 

src/northbridge/intel/ironlake/chip.h

@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H
-#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H
+#ifndef NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H
+#define NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H
 
 #include <drivers/intel/gma/i915.h>
 
@@ -25,7 +25,7 @@
  *  0x06 = Enabled, 6ms short pulse
  *  0x07 = Enabled, 100ms short pulse
  */
-struct northbridge_intel_nehalem_config {
+struct northbridge_intel_ironlake_config {
 	u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
 	u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
 	u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
@@ -48,4 +48,4 @@ struct northbridge_intel_nehalem_config {
 	u16 pci_mmio_size;
 };
 
-#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */
+#endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */

src/northbridge/intel/ironlake/early_init.c

@@ -26,9 +26,9 @@
 #include <cpu/intel/turbo.h>
 #include <arch/cpu.h>
 
-#include "nehalem.h"
+#include "ironlake.h"
 
-static void nehalem_setup_bars(void)
+static void ironlake_setup_bars(void)
 {
 	/* Setting up Southbridge. In the northbridge code. */
 	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
@@ -114,7 +114,7 @@ static void early_cpu_init (void)
 	wrmsr(IA32_MISC_ENABLE, m);
 }
 
-void nehalem_early_initialization(int chipset_type)
+void ironlake_early_initialization(int chipset_type)
 {
 	u32 capid0_a;
 	u8 reg8;
@@ -126,14 +126,14 @@ void nehalem_early_initialization(int chipset_type)
 		reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
 		reg8 &= ~7;	/* Clear 2:0 */
 
-		if (chipset_type == NEHALEM_MOBILE)
+		if (chipset_type == IRONLAKE_MOBILE)
 			reg8 |= 1;	/* Set bit 0 */
 
 		pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
 	}
 
 	/* Setup all BARs required for early PCIe and raminit */
-	nehalem_setup_bars();
+	ironlake_setup_bars();
 
 	s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
 	    (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3);

src/northbridge/intel/ironlake/finalize.c

@@ -14,11 +14,11 @@
  * GNU General Public License for more details.
  */
 
-#include "nehalem.h"
+#include "ironlake.h"
 
 #define PCI_DEV_SNB PCI_DEV(0, 0, 0)
 
-void intel_nehalem_finalize_smm(void)
+void intel_ironlake_finalize_smm(void)
 {
 	MCHBAR32_OR(0x5500, 1 << 0);	/* PAVP */
 	MCHBAR32_OR(0x5f00, 1 << 31);	/* SA PM */

src/northbridge/intel/ironlake/gma.c

@@ -33,7 +33,7 @@
 #include <types.h>
 
 #include "chip.h"
-#include "nehalem.h"
+#include "ironlake.h"
 
 /* some vga option roms are used for several chipsets but they only have one
  * PCI ID in their header. If we encounter such an option rom, we need to do
@@ -93,7 +93,7 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
 
 static void gma_pm_init_post_vbios(struct device *dev)
 {
-	struct northbridge_intel_nehalem_config *conf = dev->chip_info;
+	struct northbridge_intel_ironlake_config *conf = dev->chip_info;
 	u32 reg32;
 
 	printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
@@ -177,7 +177,7 @@ static void gma_func0_init(struct device *dev)
 
 	if (!acpi_is_wakeup_s3() &&
 	    CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
-		struct northbridge_intel_nehalem_config *conf = dev->chip_info;
+		struct northbridge_intel_ironlake_config *conf = dev->chip_info;
 		int lightup_ok;
 		printk(BIOS_SPEW, "Initializing VGA without OPROM.");
 
@@ -223,7 +223,7 @@ intel_gma_get_controller_info(void)
 	if (!dev) {
 		return NULL;
 	}
-	struct northbridge_intel_nehalem_config *chip = dev->chip_info;
+	struct northbridge_intel_ironlake_config *chip = dev->chip_info;
 	return &chip->gfx;
 }
 

src/northbridge/intel/ironlake/ironlake.h

@@ -15,8 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
-#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
+#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
+#define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
 
 #ifndef __ASSEMBLER__
 
@@ -99,9 +99,9 @@ typedef struct {
 #define D1F0_VC0RCTL 0x114
 
 /* Chipset types */
-#define NEHALEM_MOBILE	0
-#define NEHALEM_DESKTOP	1
-#define NEHALEM_SERVER	2
+#define IRONLAKE_MOBILE	0
+#define IRONLAKE_DESKTOP	1
+#define IRONLAKE_SERVER	2
 
 /* Device ID for SandyBridge and IvyBridge */
 #define BASE_REV_SNB	0x00
@@ -249,14 +249,14 @@ typedef struct {
 #define PCI_DEVICE_ID_SB 0x0104
 #define PCI_DEVICE_ID_IB 0x0154
 
-void intel_nehalem_finalize_smm(void);
+void intel_ironlake_finalize_smm(void);
 
 int bridge_silicon_revision(void);
-void nehalem_early_initialization(int chipset_type);
-void nehalem_late_initialization(void);
+void ironlake_early_initialization(int chipset_type);
+void ironlake_late_initialization(void);
 void mainboard_pre_raminit(void);
 void mainboard_get_spd_map(u8 *spd_addrmap);
 
 #endif
 #endif
-#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */
+#endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */

src/northbridge/intel/ironlake/memmap.c

@@ -23,7 +23,7 @@
 #include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <cpu/intel/smm_reloc.h>
-#include "nehalem.h"
+#include "ironlake.h"
 
 static uintptr_t smm_region_start(void)
 {

src/northbridge/intel/ironlake/northbridge.c

@@ -26,7 +26,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include "chip.h"
-#include "nehalem.h"
+#include "ironlake.h"
 #include <cpu/intel/smm_reloc.h>
 
 static int bridge_revision_id = -1;
@@ -228,7 +228,7 @@ static void northbridge_init(struct device *dev)
 }
 
 /* Disable unused PEG devices based on devicetree before PCI enumeration */
-static void nehalem_init(void *const chip_info)
+static void ironlake_init(void *const chip_info)
 {
 	u32 deven_mask = UINT32_MAX;
 	const struct device *dev;
@@ -287,8 +287,8 @@ static void enable_dev(struct device *dev)
 	}
 }
 
-struct chip_operations northbridge_intel_nehalem_ops = {
+struct chip_operations northbridge_intel_ironlake_ops = {
 	CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge")
 	.enable_dev = enable_dev,
-	.init = nehalem_init,
+	.init = ironlake_init,
 };

src/northbridge/intel/ironlake/raminit.c

@@ -41,7 +41,7 @@
 #include <types.h>
 
 #include "chip.h"
-#include "nehalem.h"
+#include "ironlake.h"
 #include "raminit.h"
 #include "raminit_tables.h"
 
@@ -1362,7 +1362,7 @@ static void program_board_delay(struct raminfo *info)
 static unsigned int get_mmio_size(void)
 {
 	const struct device *dev;
-	const struct northbridge_intel_nehalem_config *cfg = NULL;
+	const struct northbridge_intel_ironlake_config *cfg = NULL;
 
 	dev = pcidev_path_on_root(HOST_BRIDGE);
 	if (dev)

src/northbridge/intel/ironlake/raminit.h

@@ -16,7 +16,7 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
-#include "nehalem.h"
+#include "ironlake.h"
 
 void chipset_init(const int s3resume);
 /* spd_addrmap is array of 4 elements:

src/northbridge/intel/ironlake/romstage.c

@@ -22,12 +22,12 @@
 #include <cpu/x86/lapic.h>
 #include <timestamp.h>
 #include <romstage_handoff.h>
-#include "nehalem.h"
+#include "ironlake.h"
 #include <arch/romstage.h>
 #include <device/pci_def.h>
 #include <device/device.h>
-#include <northbridge/intel/nehalem/chip.h>
-#include <northbridge/intel/nehalem/raminit.h>
+#include <northbridge/intel/ironlake/chip.h>
+#include <northbridge/intel/ironlake/raminit.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <southbridge/intel/ibexpeak/pch.h>
 #include <southbridge/intel/ibexpeak/me.h>
@@ -44,7 +44,7 @@ void mainboard_romstage_entry(void)
 	enable_lapic();
 
 	/* TODO, make this configurable */
-	nehalem_early_initialization(NEHALEM_MOBILE);
+	ironlake_early_initialization(IRONLAKE_MOBILE);
 
 	early_pch_init();
 

src/northbridge/intel/ironlake/smi.c

@@ -16,7 +16,7 @@
 #include <types.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include "nehalem.h"
+#include "ironlake.h"
 
 #include <cpu/intel/smm_reloc.h>
 

src/southbridge/intel/common/firmware/Kconfig

@@ -59,7 +59,7 @@ config ME_BIN_PATH
 config CHECK_ME
 	bool "Verify the integrity of the supplied ME/TXE firmware"
 	default n
-	depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \
+	depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \
 		NORTHBRIDGE_INTEL_SANDYBRIDGE || \
 		NORTHBRIDGE_INTEL_HASWELL || \
 		SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \
@@ -71,7 +71,7 @@ config CHECK_ME
 
 config USE_ME_CLEANER
 	bool "Strip down the Intel ME/TXE firmware"
-	depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \
+	depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \
 		NORTHBRIDGE_INTEL_SANDYBRIDGE || \
 		NORTHBRIDGE_INTEL_HASWELL || \
 		SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \

src/southbridge/intel/ibexpeak/early_cir.c

@@ -14,7 +14,7 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include "pch.h"
 
 /* This sets up magic Chipset Initialization Registers */
@@ -53,7 +53,7 @@ void pch_setup_cir(int chipset_type)
 
 	/* Intel 5 Series Chipset and Intel 3400 Series Chipset
 	   External Design Specification (EDS) 13.8.1.1 */
-	if (chipset_type == NEHALEM_DESKTOP)
+	if (chipset_type == IRONLAKE_DESKTOP)
 		pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3);
 
 	pci_write_config8(PCH_LPC_DEV, CIR4, 0x45);

src/southbridge/intel/ibexpeak/early_pch.c

@@ -19,7 +19,7 @@
 #include <stdint.h>
 #include <device/pci_ops.h>
 #include <device/smbus_host.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include <southbridge/intel/ibexpeak/pch.h>
 #include <southbridge/intel/common/gpio.h>
 
@@ -47,7 +47,7 @@ void early_pch_init(void)
 	early_gpio_init();
 	enable_smbus();
 	/* TODO, make this configurable */
-	pch_setup_cir(NEHALEM_MOBILE);
+	pch_setup_cir(IRONLAKE_MOBILE);
 	southbridge_configure_default_intmap();
 	pch_default_disable();
 	early_usb_init(mainboard_usb_ports);

src/southbridge/intel/ibexpeak/smihandler.c

@@ -34,7 +34,7 @@
  *  1. the chipset can do it
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmutil.h>
 
@@ -185,6 +185,6 @@ void southbridge_finalize_all(void)
 {
 	intel_me_finalize_smm();
 	intel_pch_finalize_smm();
-	intel_nehalem_finalize_smm();
+	intel_ironlake_finalize_smm();
 	intel_model_2065x_finalize_smm();
 }

util/docker/coreboot.org-status/board-status.html/tohtml.sh

@@ -470,7 +470,7 @@ EOF
 				;;
 			"")
 				case $northbridge in
-					INTEL_NEHALEM)
+					INTEL_IRONLAKE)
 						cpu_nice="Intel® 1st Gen (Nehalem) Core i3/i5/i7"
 						socket_nice="?";;
 					RDC_R8610)