diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 9b5bd4af5e..c2f66a43eb 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE
 	select EC_GOOGLE_CHROMEEC_ESPI
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_SPI_TPM_CR50
 	select MAINBOARD_HAS_TPM2
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index e98b686608..4b2a3c5b13 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -49,7 +49,7 @@ chip soc/intel/tigerlake
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
 	}"
 
 	# Intel Common SoC Config
@@ -91,7 +91,7 @@ chip soc/intel/tigerlake
 		device pci 17.0 off end # SATA
 		device pci 19.0 off end # I2C 4
 		device pci 19.1 off end # I2C 5
-		device pci 19.2 off end # UART 2
+		device pci 19.2 on  end # UART 2
 		device pci 1a.0 off end # eMMC
 		device pci 1c.0 off end # PCI Express Root Port 1
 		device pci 1c.1 off end # PCI Express Root Port 2
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c
index b9d77bf585..c334f1107a 100644
--- a/src/mainboard/google/dedede/variants/baseboard/gpio.c
+++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c
@@ -32,6 +32,15 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+
+	/* C20 : UART_DBG_TX_AP_RX */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* C21 : UART_AP_TX_DBG_RX */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* C22 : UART2_RTS_N */
+	PAD_NC(GPP_C22, DN_20K),
+	/* C23 : UART2_CTS_N */
+	PAD_NC(GPP_C23, DN_20K),
 };
 
 /* Early pad configuration in bootblock */