soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration

TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47436
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sridhar Siricilla 2020-11-09 12:13:22 +05:30 committed by Subrata Banik
parent 3a873b5c9a
commit 95ee5996f7
2 changed files with 9 additions and 0 deletions

View File

@ -90,6 +90,14 @@ struct mb_cfg {
/* Board type */ /* Board type */
uint8_t UserBd; uint8_t UserBd;
/*
* Command pins mapping for Controller Channel (ccc)
* lp5_ccc_config: Bitmask where bits [3:0] are Controller 0 Channel [3:0] and
* bits [7:4] are Controller 1 Channel [3:0]
* Bit value: 0 = ccc pin mapping is ascending, 1 = ccc pin mapping is descending.
*/
uint8_t lp5_ccc_config;
}; };
/* /*

View File

@ -178,6 +178,7 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg,
meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated);
} }
mem_cfg->Lp5CccConfig = board_cfg->lp5_ccc_config;
mem_cfg->ECT = board_cfg->ect; mem_cfg->ECT = board_cfg->ect;
mem_cfg->UserBd = board_cfg->UserBd; mem_cfg->UserBd = board_cfg->UserBd;
mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved;