soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration

TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47436
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/include/soc/meminit.h

@@ -90,6 +90,14 @@ struct mb_cfg {
 
 	/* Board type */
 	uint8_t UserBd;
+
+	/*
+	 * Command pins mapping for Controller Channel (ccc)
+	 * lp5_ccc_config: Bitmask where bits [3:0] are Controller 0 Channel [3:0] and
+	 * bits [7:4] are Controller 1 Channel [3:0]
+	 * Bit value: 0 = ccc pin mapping is ascending, 1 = ccc pin mapping is descending.
+	 */
+	uint8_t lp5_ccc_config;
 };
 
 /*

src/soc/intel/alderlake/meminit.c

@@ -178,6 +178,7 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg,
 		meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated);
 	}
 
+	mem_cfg->Lp5CccConfig = board_cfg->lp5_ccc_config;
 	mem_cfg->ECT = board_cfg->ect;
 	mem_cfg->UserBd = board_cfg->UserBd;
 	mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved;