From 9612a3c32a95791c1084ade5ae89e9147b2c2b7b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 16 Dec 2019 05:46:16 +0100 Subject: [PATCH] cpu/intel: Remove ROMCC header guards and code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel's platforms use a GCC compiled bootblock. Change-Id: I779d7115fee75df9356873e9cc66d43280821812 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37758 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Nico Huber --- src/cpu/intel/car/non-evict/cache_as_ram.S | 3 --- src/cpu/intel/car/romstage.c | 13 ------------- src/cpu/intel/microcode/Kconfig | 2 +- src/cpu/intel/microcode/microcode.c | 18 +----------------- 4 files changed, 2 insertions(+), 34 deletions(-) diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c42df..4dee0a8002 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -28,11 +28,8 @@ _cache_as_ram_setup: bootblock_pre_c_entry: - -#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ -#endif cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a10e..bd6a5a9b8c 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,19 +71,6 @@ static void romstage_main(unsigned long bist) /* We do not return here. */ } -#if CONFIG(ROMCC_BOOTBLOCK) -/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - timestamp_init(base_timestamp); - timestamp_add_now(TS_START_ROMSTAGE); - romstage_main(bist); -} -#endif - - /* We don't carry BIST from bootblock in a good location to read from. * Any error should have been reported in bootblock already. */ diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 73afe0bb45..238aad745d 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if !ROMCC_BOOTBLOCK + default y help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 80470bf236..90138be236 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -15,11 +15,7 @@ #include #include -#if !defined(__ROMCC__) #include -#else -#include -#endif #include #include #include @@ -141,22 +137,11 @@ const void *intel_microcode_find(void) unsigned int x86_model, x86_family; msr_t msr; -#ifdef __ROMCC__ - struct cbfs_file *microcode_file; - - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); - if (!microcode_file) - return NULL; - - ucode_updates = CBFS_SUBHEADER(microcode_file); - microcode_len = ntohl(microcode_file->len); -#else ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, CBFS_TYPE_MICROCODE, µcode_len); if (ucode_updates == NULL) return NULL; -#endif /* CPUID sets MSR 0x8B if a microcode update has been loaded. */ msr.lo = 0; @@ -201,8 +186,7 @@ const void *intel_microcode_find(void) microcode_len -= update_size; } - /* ROMCC doesn't like NULL. */ - return (void *)0; + return NULL; } void intel_update_microcode_from_cbfs(void)