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mb/google/rex/var/screebo: Change sdcard clk from 7 to 6 

Update firmware to reflect schematics change for SD Card CLKSRC
from 7 to 6 for EVT board revision

BUG=b:291051683
TEST=emerge-rex coreboot

Change-Id: I3347f739650458c833d5a825742cf1d663853cc5
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kun Liu 2023-08-07 16:16:18 +08:00 committed by Subrata Banik
parent fdb3d07502
commit 961a88a115
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/google/rex/variants/screebo/overridetree.cb
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@ -245,17 +245,17 @@ chip soc/intel/meteorlake
end end
end # PCIE4_P9 SSD card end # PCIE4_P9 SSD card
device ref pcie_rp10 on device ref pcie_rp10 on
# Enable SD Card PCIE4 rp10 using clk 7 # Enable SD Card PCIE4 rp10 using clk 6
register "pcie_rp[PCH_RP(10)]" = "{ register "pcie_rp[PCH_RP(10)]" = "{
.clk_src = 7, .clk_src = 6,
.clk_req = 7, .clk_req = 6,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L1, .pcie_rp_aspm = ASPM_L1,
}" }"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)"
register "srcclk_pin" = "7" register "srcclk_pin" = "6"
device generic 0 on device generic 0 on
probe DB_SD SD_GL9750 probe DB_SD SD_GL9750
probe DB_SD SD_RTS5227S probe DB_SD SD_RTS5227S