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mb/google/rex: Update Flash Layout to fit WP_RO within 4MB 

This patch updates the Rex flash layout to optimize WP_RO to 4MB.

The idea is to create more space inside FW_RW_A/B to accommodate
multiple blobs to boot google/rex with different Intel MTL SoC stepping.

Changes for chromeos.fmd:

SI_BIOS:
     RW_SECTION_A/B: Reduce to 7MB.
     RW_LEGACY: Reduce to 1MB.
     RW_MISC: Increased to 1MB.
     RW_UNUSED: 3MB (reserved)
     WP_RO: Reduce to 4MB

Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.

BUG=b:277143384
TEST=Able to build and boot google/rex with FSP release and debug image.

Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74229
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2023-04-06 15:12:22 +05:30
parent cda48b297c
commit 9629f94c4e
1 changed files with 22 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
src/mainboard/google/rex/chromeos.fmd
View File

@ -4,38 +4,45 @@ FLASH 32M {
SI_ME SI_ME
} }
SI_BIOS 23M { SI_BIOS 23M {
RW_SECTION_A 7092K { RW_SECTION_A 7M {
VBLOCK_A 8K VBLOCK_A 8K
FW_MAIN_A(CBFS) FW_MAIN_A(CBFS)
RW_FWID_A 64 RW_FWID_A 64
ME_RW_A(CBFS) 4400K ME_RW_A(CBFS) 4400K
} }
RW_MISC 152K {
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {
SHARED_DATA 4K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 8K
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
}
# This section starts at the 16M boundary in SPI flash. # This section starts at the 16M boundary in SPI flash.
# MTL does not support a region crossing this boundary, # MTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non- # because the SPI flash is memory-mapped into two non-
# contiguous windows. # contiguous windows.
RW_SECTION_B 7092K { RW_SECTION_B 7M {
VBLOCK_B 8K VBLOCK_B 8K
FW_MAIN_B(CBFS) FW_MAIN_B(CBFS)
RW_FWID_B 64 RW_FWID_B 64
ME_RW_B(CBFS) 4400K ME_RW_B(CBFS) 4400K
} }
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
RW_ELOG(PRESERVE) 16K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
# It is placed in the common `chromeos.fmd` file because it is only 4K and there
# is free space in the RW_MISC region that cannot be easily reclaimed because
# the RW_SECTION_B must start on the 16M boundary.
RW_SPD_CACHE(PRESERVE) 4K
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
RW_LEGACY(CBFS) 1M RW_LEGACY(CBFS) 1M
RW_UNUSED 3M
# Make WP_RO region align with SPI vendor # Make WP_RO region align with SPI vendor
# memory protected range specification. # memory protected range specification.
WP_RO 8M { WP_RO 4M {
RO_VPD(PRESERVE) 16K RO_VPD(PRESERVE) 16K
RO_GSCVD 8K RO_GSCVD 8K
RO_SECTION { RO_SECTION {