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src: Remove non-ascii characters 

Change-Id: Iedb78e24a286a51830c85724af0179995ed553be
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Martin Roth 2018-05-20 17:46:51 -06:00
parent 8f25a6680e
commit 9641a92b11
8 changed files with 19 additions and 19 deletions
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2
src/drivers/i2c/max98373/chip.h
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@ -19,7 +19,7 @@
struct drivers_i2c_max98373_config { struct drivers_i2c_max98373_config {
/* I2C Bus Frequency in Hertz (default 400kHz) */ /* I2C Bus Frequency in Hertz (default 400kHz) */
uint32_t bus_speed; uint32_t bus_speed;
/* Set ‘1’ if I2S channel size is not 32bit. */ /* Set '1' if I2S channel size is not 32bit. */
bool interleave_mode; bool interleave_mode;
/* Identifier for chips */ /* Identifier for chips */
uint32_t uid; uint32_t uid;

2
src/drivers/i2c/max98927/chip.h
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@ -19,7 +19,7 @@
struct drivers_i2c_max98927_config { struct drivers_i2c_max98927_config {
/* I2C Bus Frequency in Hertz (default 400kHz) */ /* I2C Bus Frequency in Hertz (default 400kHz) */
unsigned int bus_speed; unsigned int bus_speed;
/* Set ‘1’ if I2S channel size is not 32bit. */ /* Set '1' if I2S channel size is not 32bit. */
bool interleave_mode; bool interleave_mode;
/* Identifier for chips */ /* Identifier for chips */
unsigned int uid; unsigned int uid;

2
src/soc/intel/apollolake/include/soc/meminit.h
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@ -72,7 +72,7 @@ enum {
/* /*
* ODT settings : * ODT settings :
* If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A, and HIGH for ODT_B, * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A, and HIGH for ODT_B,
 * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A, * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,
* and LOW for ODT_B, choose ODT_AB_HIGH_LOW. * and LOW for ODT_B, choose ODT_AB_HIGH_LOW.
* *
* Note that the enum values correspond to the interpreted UPD fields * Note that the enum values correspond to the interpreted UPD fields

4
src/soc/intel/cannonlake/lockdown.c
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@ -60,8 +60,8 @@ static void dmi_lockdown_cfg(void)
* GCS.BBS: (Boot BIOS Strap) This field determines the destination * GCS.BBS: (Boot BIOS Strap) This field determines the destination
* of accesses to the BIOS memory range. * of accesses to the BIOS memory range.
* Bits Description * Bits Description
* “0b”: SPI * "0b": SPI
* “1b”: LPC/eSPI * "1b": LPC/eSPI
*/ */
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
} }

4
src/soc/intel/skylake/lockdown.c
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@ -57,8 +57,8 @@ static void dmi_lockdown_config(void)
* GCS.BBS: (Boot BIOS Strap) This field determines the destination * GCS.BBS: (Boot BIOS Strap) This field determines the destination
* of accesses to the BIOS memory range. * of accesses to the BIOS memory range.
* Bits Description * Bits Description
* “0b”: SPI * "0b": SPI
* “1b”: LPC/eSPI * "1b": LPC/eSPI
*/ */
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
} }

2
src/soc/rockchip/rk3399/Kconfig
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@ -32,7 +32,7 @@ config RK3399_SPREAD_SPECTRUM_DDR
default n default n
help help
Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit
used to modulate the frequency of the Silicon Creations’ Fractional used to modulate the frequency of the Silicon Creations' Fractional
PLL in order to reduce EMI. PLL in order to reduce EMI.
endif endif

20
src/soc/rockchip/rk3399/clock.c
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@ -344,12 +344,12 @@ static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
/* /*
* Configure the DPLL spread spectrum feature on memory clock. * Configure the DPLL spread spectrum feature on memory clock.
* Configure sequence: * Configure sequence:
* 1. PLL been configured as frac mode, and DACPD should be set to 1’b0. * 1. PLL been configured as frac mode, and DACPD should be set to 1'b0.
* 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with * 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with
* extern wave table). * extern wave table).
* 3. set ssmod_disable_sscg = 1’b0, and set ssmod_bp = 1’b0. * 3. set ssmod_disable_sscg = 1'b0, and set ssmod_bp = 1'b0.
* 4. Assert RESET = 1’b1 to SSMOD. * 4. Assert RESET = 1'b1 to SSMOD.
* 5. RESET = 1’b0 on SSMOD. * 5. RESET = 1'b0 on SSMOD.
* 6. Adjust SPREAD/DIVVAL/DOWNSPREAD. * 6. Adjust SPREAD/DIVVAL/DOWNSPREAD.
*/ */
static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)
@ -385,13 +385,13 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)
* value of SPREAD. * value of SPREAD.
* SPREAD[4:0] Center Spread Down Spread * SPREAD[4:0] Center Spread Down Spread
* 0 0 0 * 0 0 0
* 1 ±0.1% -0.10% * 1 +/-0.1% -0.10%
* 2 ±0.2% -0.20% * 2 +/-0.2% -0.20%
* 3 ±0.3% -0.30% * 3 +/-0.3% -0.30%
* 4 ±0.4% -0.40% * 4 +/-0.4% -0.40%
* 5 ±0.5% -0.50% * 5 +/-0.5% -0.50%
* ... * ...
* 31 ±3.1% -3.10% * 31 +/-3.1% -3.10%
*/ */
write32(&cru_ptr->dpll_con[4], write32(&cru_ptr->dpll_con[4],
RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT, RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT,

2
src/southbridge/via/vt8237r/acpi/default_irq_route.asl
View File

@ -71,7 +71,7 @@ Method (_PRT, 0) {
Package (4) { 0x0010ffff, 2, 0x00, 21 }, Package (4) { 0x0010ffff, 2, 0x00, 21 },
Package (4) { 0x0010ffff, 3, 0x00, 21 }, Package (4) { 0x0010ffff, 3, 0x00, 21 },
/* AC’97 / MC’97 IRQ and INTG => IRQ22 */ /* AC'97 / MC'97 IRQ and INTG => IRQ22 */
Package (4) { 0x0011ffff, 0, 0x00, 22 }, Package (4) { 0x0011ffff, 0, 0x00, 22 },
Package (4) { 0x0011ffff, 1, 0x00, 22 }, Package (4) { 0x0011ffff, 1, 0x00, 22 },
Package (4) { 0x0011ffff, 2, 0x00, 22 }, Package (4) { 0x0011ffff, 2, 0x00, 22 },