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Documentation: gpio: Update table as per coreboot guidelines 

This patch fixes the table issue in markdown file introduced with commit
5338a16b (Documentation: gpio: Fix table).

BUG=b:211573253, b:211950520

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic4f27f46a9d219098612d8b7747ae26116506fce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Subrata Banik 2022-03-27 20:15:50 +05:30 committed by Felix Held
parent 812df72a54
commit 9648106683
1 changed files with 55 additions and 26 deletions
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81
Documentation/getting_started/gpio.md
View File

@ -167,32 +167,61 @@ could cause catastrophic failures, up to and including your mainboard!
As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
supports four different types of GPIO reset as: supports four different types of GPIO reset as:
| PAD Reset Config | Platform Reset | GPP | GPD | ```eval_rst
|-------------------------------------------------|----------------|-----|-----| +------------------------+----------------+-------------+-------------+
| 00 - Power Good (GPP: RSMRST, GPD: DSW_PWROK) | Warm Reset | N | N | | | | PAD Reset ? |
| | Cold Reset | N | N | + PAD Reset Config + Platform Reset +-------------+-------------+
| | S3/S4/S5 | N | N | | | | GPP | GPD |
| | Global Reset | N | N | +========================+================+=============+=============+
| | Deep Sx | Y | N | | | 00 - Power Good | Warm Reset | N | N |
| | G3 | Y | N | | | (GPP: RSMRST, +----------------+-------------+-------------+
| 01 - Deep | Warm Reset | Y | Y | | | GPD: DSW_PWROK) | Cold Reset | N | N |
| | Cold Reset | Y | Y | | |----------------+-------------+-------------+
| | S3/S4/S5 | N | N | | | S3/S4/S5 | N | N |
| | Global Reset | Y | Y | | +----------------+-------------+-------------+
| | Deep Sx | Y | Y | | | Global Reset | N | N |
| | G3 | Y | Y | | +----------------+-------------+-------------+
| 10 - Host Reset/PLTRST | Warm Reset | Y | Y | | | Deep Sx | Y | N |
| | Cold Reset | Y | Y | | +----------------+-------------+-------------+
| | S3/S4/S5 | Y | Y | | | G3 | Y | Y |
| | Global Reset | Y | Y | +------------------------+----------------+-------------+-------------+
| | Deep Sx | Y | Y | | 01 - Deep | Warm Reset | Y | Y |
| | G3 | Y | Y | | +----------------+-------------+-------------+
| 11 - Resume Reset (GPP: Reserved, GPD: RSMRST) | Warm Reset | - | N | | | Cold Reset | Y | Y |
| | Cold Reset | - | N | | +----------------+-------------+-------------+
| | S3/S4/S5 | - | N | | | S3/S4/S5 | N | N |
| | Global Reset | - | N | | +----------------+-------------+-------------+
| | Deep Sx | - | Y | | | Global Reset | Y | Y |
| | G3 | - | Y | | +----------------+-------------+-------------+
| | Deep Sx | Y | Y |
| +----------------+-------------+-------------+
| | G3 | Y | Y |
+------------------------+----------------+-------------+-------------+
| 10 - Host Reset/PLTRST | Warm Reset | Y | Y |
| +----------------+-------------+-------------+
| | Cold Reset | Y | Y |
| +----------------+-------------+-------------+
| | S3/S4/S5 | Y | Y |
| +----------------+-------------+-------------+
| | Global Reset | Y | Y |
| +----------------+-------------+-------------+
| | Deep Sx | Y | Y |
| +----------------+-------------+-------------+
| | G3 | Y | Y |
+------------------------+----------------+-------------+-------------+
| | 11 - Resume Reset | Warm Reset | - | N |
| | (GPP: Reserved, +----------------+-------------+-------------+
| | GPD: RSMRST) | Cold Reset | - | N |
| +----------------+-------------+-------------+
| | S3/S4/S5 | - | N |
| +----------------+-------------+-------------+
| | Global Reset | - | N |
| +----------------+-------------+-------------+
| | Deep Sx | - | Y |
| +----------------+-------------+-------------+
| | G3 | - | Y |
+------------------------+----------------+-------------+-------------+
```
Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
specific register fields in the PAD configuration register. specific register fields in the PAD configuration register.