nb/intel/sandybridge: Clean up stepping logic
Do not combine the host bridge device ID with the CPU stepping because it is confusing. Although Sandy/Ivy Bridge processors incorporate both CPU and northbridge components into the same die, it is best to treat them separately. Plus, this change enables moving CPU stepping macros from northbridge code into the CPU scope, which is done in a follow-up. Change-Id: I27ad609eb53b96987ad5445301b5392055fa4ea1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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Angel Pons
parent
927b1c0161
commit
964d91f7d7
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@ -3,6 +3,7 @@
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#ifndef _CPU_INTEL_MODEL_206AX_H
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#define _CPU_INTEL_MODEL_206AX_H
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#include <arch/cpu.h>
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#include <stdint.h>
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/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
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@ -88,4 +89,9 @@ void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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int get_platform_id(void);
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static inline u8 cpu_stepping(void)
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{
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return cpuid_eax(1) & 0xf;
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}
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#endif
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@ -4,6 +4,7 @@
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#include <device/mmio.h>
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#include <console/console.h>
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#include <bootmode.h>
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#include <cpu/intel/model_206ax/model_206ax.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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@ -301,6 +302,8 @@ int gtt_poll(u32 reg, u32 mask, u32 value)
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static void gma_pm_init_pre_vbios(struct device *dev)
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{
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const bool is_sandy = is_sandybridge();
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u32 reg32;
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printk(BIOS_DEBUG, "GT Power Management Init\n");
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@ -309,7 +312,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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if (!gtt_res || !gtt_res->base)
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return;
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if (bridge_silicon_revision() < IVB_STEP_C0) {
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if (is_sandy || cpu_stepping() < IVB_STEP_C0) {
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/* 1: Enable force wake */
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gtt_write(0xa18c, 0x00000001);
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gtt_poll(0x130090, (1 << 0), (1 << 0));
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@ -319,14 +322,14 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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gtt_poll(0x130040, (1 << 0), (1 << 0));
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}
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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if (is_sandy) {
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/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
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reg32 = gtt_read(0x42004);
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reg32 |= (1 << 14) | (1 << 15);
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gtt_write(0x42004, reg32);
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}
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if (bridge_silicon_revision() >= IVB_STEP_A0) {
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if (!is_sandy) {
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/* Display Reset Acknowledge Settings */
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reg32 = gtt_read(0x45010);
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reg32 |= (1 << 1) | (1 << 0);
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@ -335,7 +338,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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/* 2: Get GT SKU from GTT+0x911c[13] */
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reg32 = gtt_read(0x911c);
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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if (is_sandy) {
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if (reg32 & (1 << 13)) {
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printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n");
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gtt_write_powermeter(snb_pm_gt1);
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@ -384,13 +387,12 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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reg32 = gtt_read(0xa180);
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reg32 |= (1 << 26) | (1 << 31);
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/* (bit 20=1 for SNB step D1+ / IVB A0+) */
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if (bridge_silicon_revision() >= SNB_STEP_D1)
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if (!is_sandy || cpu_stepping() >= SNB_STEP_D1)
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reg32 |= (1 << 20);
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gtt_write(0xa180, reg32);
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/* 6a: for SnB step D2+ only */
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if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
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(bridge_silicon_revision() >= SNB_STEP_D2)) {
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if (is_sandy && cpu_stepping() >= SNB_STEP_D2) {
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reg32 = gtt_read(0x9400);
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reg32 |= (1 << 7);
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gtt_write(0x9400, reg32);
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@ -402,16 +404,16 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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gtt_poll(0x941c, (1 << 1), (0 << 1));
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}
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
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if (is_sandy) {
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/* 6b: Clocking reset controls */
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gtt_write(0x9424, 0x00000000);
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} else {
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reg32 = gtt_read(0x907c);
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reg32 |= (1 << 16);
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gtt_write(0x907c, reg32);
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/* 6b: Clocking reset controls */
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gtt_write(0x9424, 0x00000001);
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} else {
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/* 6b: Clocking reset controls */
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gtt_write(0x9424, 0x00000000);
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}
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/* 7 */
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@ -503,7 +505,7 @@ static void gma_pm_init_post_vbios(struct device *dev)
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printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
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/* 15: Deassert Force Wake */
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if (bridge_silicon_revision() < IVB_STEP_C0) {
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if (is_sandybridge() || cpu_stepping() < IVB_STEP_C0) {
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gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
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gtt_poll(0x130090, (1 << 0), (0 << 0));
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} else {
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@ -4,31 +4,26 @@
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#include <acpi/acpi.h>
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#include <commonlib/helpers.h>
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#include <device/pci_ops.h>
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#include <stdint.h>
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#include <delay.h>
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#include <cpu/intel/model_206ax/model_206ax.h>
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <types.h>
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#include "chip.h"
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#include "sandybridge.h"
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#include <cpu/intel/smm_reloc.h>
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static int bridge_revision_id = -1;
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/* IGD UMA memory */
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static uint64_t uma_memory_base = 0;
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static uint64_t uma_memory_size = 0;
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int bridge_silicon_revision(void)
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bool is_sandybridge(void)
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{
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if (bridge_revision_id < 0) {
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uint8_t stepping = cpuid_eax(1) & 0x0f;
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uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID);
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bridge_revision_id = (bridge_id & 0xf0) | stepping;
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}
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return bridge_revision_id;
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const uint16_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID);
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return (bridge_id & BASE_REV_MASK) == BASE_REV_SNB;
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}
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/* Reserve everything between A segment and 1MB:
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@ -115,7 +110,7 @@ static void add_fixed_resources(struct device *dev, int index)
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CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
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#endif
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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if (is_sandybridge()) {
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/* Required for SandyBridge sighting 3715511 */
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bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
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bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
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@ -259,6 +254,8 @@ static void mc_read_resources(struct device *dev)
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static void northbridge_dmi_init(struct device *dev)
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{
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const bool is_sandy = is_sandybridge();
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u32 reg32;
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/* Clear error status bits */
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@ -266,7 +263,7 @@ static void northbridge_dmi_init(struct device *dev)
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DMIBAR32(DMICESTS) = 0xffffffff;
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/* Steps prior to DMI ASPM */
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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if (is_sandy) {
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reg32 = DMIBAR32(0x250);
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reg32 &= ~((1 << 22) | (1 << 20));
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reg32 |= (1 << 21);
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@ -277,12 +274,12 @@ static void northbridge_dmi_init(struct device *dev)
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reg32 |= (1 << 29);
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DMIBAR32(DMILLTC) = reg32;
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if (bridge_silicon_revision() >= SNB_STEP_D0) {
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if (!is_sandy || cpu_stepping() >= SNB_STEP_D0) {
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reg32 = DMIBAR32(0x1f8);
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reg32 |= (1 << 16);
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DMIBAR32(0x1f8) = reg32;
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} else if (bridge_silicon_revision() >= SNB_STEP_D1) {
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} else if (!is_sandy || cpu_stepping() >= SNB_STEP_D1) {
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reg32 = DMIBAR32(0x1f8);
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reg32 &= ~(1 << 26);
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reg32 |= (1 << 16);
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@ -294,7 +291,7 @@ static void northbridge_dmi_init(struct device *dev)
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}
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/* Enable ASPM on SNB link, should happen before PCH link */
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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if (is_sandy) {
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reg32 = DMIBAR32(0xd04);
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reg32 |= (1 << 4);
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DMIBAR32(0xd04) = reg32;
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@ -376,7 +373,10 @@ static void northbridge_init(struct device *dev)
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bridge_type = MCHBAR32(SAPMTIMERS);
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bridge_type &= ~0xff;
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
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if (is_sandybridge()) {
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/* 20h for Sandybridge */
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bridge_type |= 0x20;
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} else {
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/* Enable Power Aware Interrupt Routing */
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u8 pair = MCHBAR8(INTRDIRCTL);
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pair &= ~0x0f; /* Clear 3:0 */
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@ -385,9 +385,6 @@ static void northbridge_init(struct device *dev)
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/* 30h for IvyBridge */
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bridge_type |= 0x30;
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} else {
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/* 20h for Sandybridge */
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bridge_type |= 0x20;
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}
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MCHBAR32(SAPMTIMERS) = bridge_type;
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@ -9,22 +9,22 @@
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#define BASE_REV_MASK 0x50
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/* SandyBridge CPU stepping */
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#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
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#define SNB_STEP_D1 (BASE_REV_SNB + 6)
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#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
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#define SNB_STEP_D0 5 /* Also J0 */
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#define SNB_STEP_D1 6
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#define SNB_STEP_D2 7 /* Also J1/Q0 */
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/* IvyBridge CPU stepping */
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#define IVB_STEP_A0 (BASE_REV_IVB + 0)
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#define IVB_STEP_B0 (BASE_REV_IVB + 2)
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#define IVB_STEP_C0 (BASE_REV_IVB + 4)
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#define IVB_STEP_K0 (BASE_REV_IVB + 5)
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#define IVB_STEP_D0 (BASE_REV_IVB + 6)
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#define IVB_STEP_A0 0
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#define IVB_STEP_B0 2
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#define IVB_STEP_C0 4
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#define IVB_STEP_K0 5
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#define IVB_STEP_D0 6
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#include "memmap.h"
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/* Everything below this line is ignored in the DSDT */
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#ifndef __ACPI__
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#include <stdint.h>
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#include <types.h>
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/* Chipset types */
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enum platform_type {
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@ -87,8 +87,9 @@ enum platform_type {
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#ifndef __ASSEMBLER__
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bool is_sandybridge(void);
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void intel_sandybridge_finalize_smm(void);
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int bridge_silicon_revision(void);
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void systemagent_early_init(void);
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void sandybridge_init_iommu(void);
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void sandybridge_late_initialization(void);
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