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amd/family_10h-family_15h: Fix poor performance on Family 15h CPUs 

Change-Id: Ieb1f1fb5653651c98764de79636669802578d5f9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12028
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson 2015-08-07 19:04:49 -05:00 committed by Martin Roth
parent caf0adac4f
commit 965704a962
2 changed files with 52 additions and 6 deletions
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13
src/cpu/amd/family_10h-family_15h/defaults.h
View File

@ -518,15 +518,15 @@ static const struct {
{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL, { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00800756, 0x00F3FFFF }, 0x00800756, 0x00F3FFFF },
{ 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00a11755, 0x00f3ffff },
{ 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA, { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x00C37756, 0x00F3FFFF }, 0x00C37756, 0x00F3FFFF },
{ 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA, { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x00000036, 0x000000FF }, 0x00000036, 0x000000FF },
{ 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00a11755, 0x00f3ffff },
/* Errata 281 Workaround */ /* Errata 281 Workaround */
{ 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1), { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
AMD_PTYPE_SVR, 0x00000001, 0x0000000F }, AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
@ -538,6 +538,13 @@ static const struct {
{ 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA, { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA,
0x8000052A, 0xD5FFFFFF }, 0x8000052A, 0xD5FFFFFF },
/* Core Interface Buffer Count */
{ 3, 0x1a0, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00034004, 0x00037007 }, /* CpuToNbFreeBufCnt = 0x3,
L3ToSriReqCBC = 0x4,
L3FreeListCBC = default,
CpuCmdBufCnt = 0x4 */
/* ACPI Power State Control Reg1 */ /* ACPI Power State Control Reg1 */
{ 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL, { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0xE6002200, 0xFFFFFFFF }, 0xE6002200, 0xFFFFFFFF },

45
src/cpu/amd/family_10h-family_15h/init_cpus.c
View File

@ -844,8 +844,9 @@ static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
*/ */
static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
{ {
u32 val; uint32_t val;
u32 linktype = 0; uint32_t val2;
uint32_t linktype = 0;
/* Check connect, init and coherency */ /* Check connect, init and coherency */
val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18); val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18);
@ -860,8 +861,13 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
if (linktype) { if (linktype) {
/* Check gen3 */ /* Check gen3 */
val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08); val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08);
val = (val >> 8) & 0xf;
if (is_gt_rev_d()) {
val2 = pci_read_config32(NODE_PCI(node, 0), regoff + 0x1c);
val |= (val2 & 0x1) << 4;
}
if (((val >> 8) & 0x0F) > 6) if (val > 6)
linktype |= HTPHY_LINKTYPE_HT3; linktype |= HTPHY_LINKTYPE_HT3;
else else
linktype |= HTPHY_LINKTYPE_HT1; linktype |= HTPHY_LINKTYPE_HT1;
@ -1148,6 +1154,39 @@ static void cpuSetAMDPCI(u8 node)
pci_write_config32(NODE_PCI(node, 3), 0xd4, dword); pci_write_config32(NODE_PCI(node, 3), 0xd4, dword);
} }
if (revision & AMD_FAM15_ALL) {
uint32_t f5x80;
uint8_t cu_enabled;
uint8_t compute_unit_count = 0;
uint8_t compute_unit_buffer_count;
/* Determine the number of active compute units on this node */
f5x80 = pci_read_config32(NODE_PCI(node, 5), 0x80);
cu_enabled = f5x80 & 0xf;
if (cu_enabled == 0x1)
compute_unit_count = 1;
if (cu_enabled == 0x3)
compute_unit_count = 2;
if (cu_enabled == 0x7)
compute_unit_count = 3;
if (cu_enabled == 0xf)
compute_unit_count = 4;
if (compute_unit_count == 1)
compute_unit_buffer_count = 0x1c;
else if (compute_unit_count == 2)
compute_unit_buffer_count = 0x18;
else if (compute_unit_count == 3)
compute_unit_buffer_count = 0x14;
else
compute_unit_buffer_count = 0x10;
dword = pci_read_config32(NODE_PCI(node, 3), 0x1a0);
dword &= ~(0x1f << 4); /* L3FreeListCBC = compute_unit_buffer_count */
dword |= (compute_unit_buffer_count << 4);
pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword);
}
printk(BIOS_DEBUG, " done\n"); printk(BIOS_DEBUG, " done\n");
} }