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intel/strago: Get Boot Flash Write Protect status

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Read GPIO to get the status

Change-Id: Id2d56ce4b47c4cccba2de3f113afaee6c49885c9
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13186
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Hannah Williams 2016-01-22 23:04:05 -08:00 committed by Martin Roth
parent b1e4bd0d28
commit 9657f3bb09
1 changed files with 7 additions and 9 deletions
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16
src/mainboard/intel/strago/chromeos.c
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@ -23,12 +23,11 @@
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
#endif #endif
#include <rules.h> #include <rules.h>
#include <soc/gpio.h> #include <gpio.h>
#include <string.h> #include <string.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ #define WP_GPIO GP_E_22
#define WP_STATUS_PAD 36
#if ENV_RAMSTAGE #if ENV_RAMSTAGE
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>
@ -115,15 +114,14 @@ int get_write_protect_state(void)
{ {
/* /*
* The vboot loader queries this function in romstage. The GPIOs have * The vboot loader queries this function in romstage. The GPIOs have
* not been set up yet as that configuration is done in ramstage. The * not been set up yet as that configuration is done in ramstage.
* hardware defaults to an input but there is a 20K pulldown. Externally * Configuring this GPIO as input so that there isn't any ambiguity
* there is a 10K pullup. Disable the internal pull in romstage so that * in the reading.
* there isn't any ambiguity in the reading.
*/ */
#if ENV_ROMSTAGE #if ENV_ROMSTAGE
ssus_disable_internal_pull(WP_STATUS_PAD); gpio_input_pullup(WP_GPIO);
#endif #endif
/* WP is enabled when the pin is reading high. */ /* WP is enabled when the pin is reading high. */
return ssus_get_gpio(WP_STATUS_PAD); return !!gpio_get(WP_GPIO);
} }