Various Nokia IP530 fixes.
- Correct default ROM image size for this board (512KB is correct). - devicetree.cb: Add AUX I/O config (mainly GPIO settings). This allows you to control the LEDs in the front panel and JP900/JP901 can be read. - irq_tables.c: Rework PIRQ table to make more onboard devices work. Also, avoid IRQ9. - mainboard.c: Drop unneeded functions, everything is done in devicetree.cb. Signed-off-by: Marc Bertens <mbertens@xs4all.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Bertens
Uwe Hermann
parent
69436e1a8c
commit
965c43b4db
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@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SUPERIO_SMSC_SMSCSUPERIO
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select SOUTHBRIDGE_TI_PCI1X2X
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select DRIVERS_DEC_21143
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select BOARD_ROMSIZE_KB_256
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select BOARD_ROMSIZE_KB_512
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select PIRQ_ROUTE
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select HAVE_PIRQ_TABLE
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select UDELAY_TSC
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@ -40,10 +40,55 @@ chip northbridge/intel/i440bx # Northbridge
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.6 on end # RTC
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device pnp 3f0.7 off end # PS/2 keyboard / mouse (No connector)
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device pnp 3f0.8 on end # AUX I/O
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device pnp 3f0.a off end # ACPI (No support yet)
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device pnp 3f0.6 on # RTC
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irq 0x63 = 0x72
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end
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device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector)
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end
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device pnp 3f0.8 on # AUX I/O
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irq 0x24 = 0x84 # OSC
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irq 0xB2 = 0x0C # Soft power status 1
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irq 0xB3 = 0x05 # Soft power status 2
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irq 0xC0 = 0x03 # IRQ MUX control
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irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable
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irq 0xCA = 0x09 # GP52 = IRQ8 (output)
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irq 0xCB = 0x01 # GP53 = nROMCS (output)
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irq 0xCC = 0x11 # GP54 = (I/O) input
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irq 0xF9 = 0x00 # read/write GP5x lines (0x1C)
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irq 0xD0 = 0x08 # GP60 = IRQ1
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irq 0xD1 = 0x08 # GP61 = IRQ3
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irq 0xD2 = 0x08 # GP62 = IRQ4
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irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board
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irq 0xD4 = 0x11 # GP64 = (I/O) input
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irq 0xD5 = 0x11 # GP65 = (I/O) input
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irq 0xD6 = 0x08 # GP66 = IRQ8
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irq 0xD7 = 0x11 # GP67 = (I/O) input
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irq 0xFA = 0x00 # read/write GP6x lines (0x88)
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irq 0xE0 = 0x00 # GP10 (I/O) = output
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irq 0xE1 = 0x01 # GP11 (I/O) = input
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irq 0xE2 = 0x08 # GP12 = P17
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irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low
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irq 0xE4 = 0x00 # GP14 (I/O) = output
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irq 0xE5 = 0x00 # GP15 (I/O) = output
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irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open
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irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low
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irq 0xF6 = 0xFF # read/write GP1x lines (0xCA)
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irq 0xEF = 0x00 # GP_INT2 disable
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irq 0xF0 = 0x00 # GP_INT1 disable
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irq 0xF1 = 0x00 # WDT_UNITS
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irq 0xF2 = 0x00 # WDT_VAL
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irq 0xF3 = 0x00 # WDT_CFG
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irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt)
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end
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device pnp 3f0.a off # ACPI (No support yet)
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# irq 0x60 = 0x0C
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# irq 0x61 = 0x80
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end
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end
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end
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device pci 7.1 on end # IDE
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@ -20,6 +20,8 @@
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#include <arch/pirq_routing.h>
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#define PIRQ_IRQ_MASK 0x0c60
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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@ -31,46 +33,51 @@ const struct irq_routing_table intel_irq_routing_table = {
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0x122e, /* Device */
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0, /* Miniport */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x44, /* Checksum */
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0xD7, /* Checksum */
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{
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/**
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* Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
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* Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
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* FEDCBA9876543210
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* 0x1E20 = 0001111000100000
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* 0x0C60 = 0000110001100000
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*/
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// Southbridge 82371
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{ 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
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// Southbridge 82371EB, INTD = 0x63
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{ 0x00, (0x07 << 3) | 0x0, {{0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// On-board PCI-to-PCI bridge
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{ 0x01, (0x00 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
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// ETH1 on front panel
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{ 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
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// ETH2 on front panel
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{ 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
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// ETH3 on front panel
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{ 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
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// ETH4 on front panel
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{ 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
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// PCMCIA/Cardbus controller
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{ 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
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{ 0x01, (0x00 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// ETH1 on front panel, INTA = 0x62 = ok
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{ 0x00, (0x0d << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// ETH2 on front panel, 0x63
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{ 0x00, (0x0e << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// ETH3 on front panel = 0x60
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{ 0x02, (0x04 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// ETH4 on front panel, INTA = 0x61 = ok
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{ 0x02, (0x05 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// PCMCIA/Cardbus controller, INTA = 0x60 = ok, INTB = 0x61 = ok
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{ 0x00, (0x0f << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// Bridge for slot 1 (top)
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{ 0x02, (0x07 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x64, 0x1E20}}, 0x0, 0x0 },
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{ 0x02, (0x07 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x64, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// PCI compact slots 1 (top)
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{ 0x03, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x1, 0x0 },
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{ 0x03, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x2, 0x0 },
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{ 0x03, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x3, 0x0 },
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{ 0x03, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x4, 0x0 },
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{ 0x03, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x1, 0x0 },
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{ 0x03, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x2, 0x0 },
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{ 0x03, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x3, 0x0 },
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{ 0x03, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x4, 0x0 },
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// Bridge for slot 2 (middle)
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{ 0x02, (0x06 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
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{ 0x02, (0x06 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// PCI compact slots 2 (middle)
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{ 0x04, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x5, 0x0 },
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{ 0x04, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x6, 0x0 },
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{ 0x04, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x7, 0x0 },
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{ 0x04, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x8, 0x0 },
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{ 0x04, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x5, 0x0 },
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{ 0x04, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x6, 0x0 },
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{ 0x04, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x7, 0x0 },
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{ 0x04, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x8, 0x0 },
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// Bridge for slot 3 (bottom)
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{ 0x00, (0x10 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
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{ 0x00, (0x10 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
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// PCI compact slots 3 (bottom)
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{ 0x05, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x9, 0x0 },
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{ 0x05, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0xA, 0x0 },
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{ 0x05, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0xB, 0x0 },
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{ 0x05, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0xC, 0x0 },
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{ 0x05, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x9, 0x0 },
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{ 0x05, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0xA, 0x0 },
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{ 0x05, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0xB, 0x0 },
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{ 0x05, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0xC, 0x0 },
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}
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};
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@ -81,10 +88,9 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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/**
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* TODO: This stub function is here until the point is solved in the
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* main code of coreboot. see also arch/x86/boot/pirq_tables.c
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* main code of coreboot. See also arch/x86/boot/pirq_tables.c.
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*/
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void pirq_assign_irqs(const unsigned char pIntAtoD[4])
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{
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return;
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}
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@ -20,44 +20,7 @@
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#include <device/device.h>
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#include "chip.h"
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#include <device/pci_def.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <console/console.h>
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#define OUTB outb
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#define INB inb
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/*
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* Taken from flashrom project
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* Generic Super I/O helper functions
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*/
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static uint8_t sio_read(uint16_t port, uint8_t reg)
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{
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OUTB( reg, port );
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return ( INB( port + 1 ) );
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}
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static void sio_write(uint16_t port, uint8_t reg, uint8_t data)
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{
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OUTB( reg, port );
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OUTB( data, port + 1 );
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return;
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}
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static void nokia_ip530_board_enable( device_t dev )
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{
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print_debug( "Setting up IP530-Super I/O devices\n");
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sio_write( 0x20, 0x03, 0x80 );
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printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) );
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sio_write( 0x20, 0x22, 0x30 );
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printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) );
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sio_write( 0x20, 0x24, 0x84 );
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printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) );
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return;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("Nokia IP530 Mainboard")
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.enable_dev = nokia_ip530_board_enable,
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};
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