mediatek/mt8183: Add AUXADC driver
We plan to get board id and RAM code from AUXADC on Kukui. Add AUXADC driver to support it. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I121a6a0240f9c517c0cbc07e0c18b09167849ff1 Signed-off-by: Po Xu <jg_poxu@mediatek.com> Reviewed-on: https://review.coreboot.org/29061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -1,5 +1,6 @@
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ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)
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ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)
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bootblock-y += auxadc.c
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bootblock-y += bootblock.c
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bootblock-y += bootblock.c
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bootblock-y += ../common/gpio.c gpio.c
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bootblock-y += ../common/gpio.c gpio.c
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bootblock-y += ../common/pll.c pll.c
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bootblock-y += ../common/pll.c pll.c
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@ -14,12 +15,14 @@ decompressor-y += decompressor.c
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decompressor-y += ../common/mmu_operations.c
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decompressor-y += ../common/mmu_operations.c
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decompressor-y += ../common/timer.c
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decompressor-y += ../common/timer.c
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verstage-y += auxadc.c
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verstage-y += ../common/gpio.c gpio.c
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verstage-y += ../common/gpio.c gpio.c
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verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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verstage-y += ../common/timer.c
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verstage-y += ../common/timer.c
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verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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verstage-y += ../common/wdt.c
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verstage-y += ../common/wdt.c
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romstage-y += auxadc.c
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romstage-y += ../common/cbmem.c emi.c
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romstage-y += ../common/cbmem.c emi.c
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romstage-y += dramc_init_setting.c
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romstage-y += dramc_init_setting.c
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romstage-y += memory.c
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romstage-y += memory.c
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@ -30,6 +33,7 @@ romstage-y += ../common/timer.c
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romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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romstage-y += ../common/wdt.c
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romstage-y += ../common/wdt.c
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ramstage-y += auxadc.c
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ramstage-y += ../common/cbmem.c emi.c
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ramstage-y += ../common/cbmem.c emi.c
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ramstage-y += ../common/gpio.c gpio.c
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ramstage-y += ../common/gpio.c gpio.c
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ramstage-y += ../common/mmu_operations.c mmu_operations.c
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ramstage-y += ../common/mmu_operations.c mmu_operations.c
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@ -0,0 +1,68 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <assert.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/auxadc.h>
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#include <soc/infracfg.h>
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#include <timer.h>
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static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE;
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/*
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* Wait until a condition becomes true or times out
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*
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* cond : a C expression to wait for
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* timeout : msecs
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*/
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#define wait_ms(cond, timeout) \
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({ \
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struct stopwatch sw; \
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int expired = 0; \
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stopwatch_init_msecs_expire(&sw, timeout); \
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while (!(cond) && !(expired = stopwatch_expired(&sw))) \
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; /* wait */ \
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assert(!expired); \
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})
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static uint32_t auxadc_get_rawdata(int channel)
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{
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setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10);
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wait_ms(!(read32(&mtk_auxadc->con2) & 0x1), 300);
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clrbits_le32(&mtk_auxadc->con1, 1 << channel);
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wait_ms(!(read32(&mtk_auxadc->data[channel]) & (1 << 12)), 300);
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setbits_le32(&mtk_auxadc->con1, 1 << channel);
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udelay(25);
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wait_ms(read32(&mtk_auxadc->data[channel]) & (1 << 12), 300);
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uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF;
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setbits_le32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10);
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return value;
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}
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int auxadc_get_voltage(unsigned int channel)
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{
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assert(channel < 16);
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/* 1.5V in 4096 steps */
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return (int)((int64_t)auxadc_get_rawdata(channel) * 1500000 / 4096);
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}
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@ -32,6 +32,7 @@ enum {
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EMI_BASE = IO_PHYS + 0x00219000,
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EMI_BASE = IO_PHYS + 0x00219000,
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EMI_MPU_BASE = IO_PHYS + 0x00226000,
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EMI_MPU_BASE = IO_PHYS + 0x00226000,
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DRAMC_CH_BASE = IO_PHYS + 0x00228000,
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DRAMC_CH_BASE = IO_PHYS + 0x00228000,
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AUXADC_BASE = IO_PHYS + 0x01001000,
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UART0_BASE = IO_PHYS + 0x01002000,
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UART0_BASE = IO_PHYS + 0x01002000,
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SPI0_BASE = IO_PHYS + 0x0100A000,
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SPI0_BASE = IO_PHYS + 0x0100A000,
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SPI1_BASE = IO_PHYS + 0x01010000,
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SPI1_BASE = IO_PHYS + 0x01010000,
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@ -0,0 +1,34 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MTK_ADC_H
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#define _MTK_ADC_H
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#include <stdint.h>
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typedef struct mtk_auxadc_regs {
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uint32_t con0;
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uint32_t con1;
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uint32_t con1_set;
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uint32_t con1_clr;
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uint32_t con2;
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uint32_t data[16];
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uint32_t reserved[16];
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uint32_t misc;
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} mtk_auxadc_regs;
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/* Return voltage in uVolt */
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int auxadc_get_voltage(unsigned int channel);
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#endif
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