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break the tree really quick due to svn restrictions, next commit fill fix it 

again.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2006-04-06 21:37:10 +00:00
parent 44f72eb3a3
commit 966d0e6d70
43 changed files with 136 additions and 1042 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/dell/s1850/Config.lb
View File

@ -134,7 +134,7 @@ config chip.h
chip northbridge/intel/E7520 # mch chip northbridge/intel/E7520 # mch
device pci_domain 0 on device pci_domain 0 on
chip southbridge/intel/ich5r # ich5r chip southbridge/intel/i82801er # i82801er
# USB ports # USB ports
device pci 1d.0 on end device pci 1d.0 on end
device pci 1d.1 on end device pci 1d.1 on end

2
src/mainboard/dell/s1850/auto.c
View File

@ -10,7 +10,7 @@
#include "pc80/serial.c" #include "pc80/serial.c"
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#include "southbridge/intel/ich5r/ich5r_early_smbus.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/E7520/raminit.h" #include "northbridge/intel/E7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h" #include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/intel/jarrell/Config.lb
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@ -151,7 +151,7 @@ chip northbridge/intel/E7520
end end
end end
device pci 06.0 on end device pci 06.0 on end
chip southbridge/intel/ich5r # ich5r chip southbridge/intel/i82801er # i82801er
device pci 1d.0 on end device pci 1d.0 on end
device pci 1d.1 on end device pci 1d.1 on end
device pci 1d.2 on end device pci 1d.2 on end

2
src/mainboard/intel/jarrell/auto.c
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@ -10,7 +10,7 @@
#include "pc80/serial.c" #include "pc80/serial.c"
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#include "southbridge/intel/ich5r/ich5r_early_smbus.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/E7520/raminit.h" #include "northbridge/intel/E7520/raminit.h"
#include "superio/NSC/pc87427/pc87427.h" #include "superio/NSC/pc87427/pc87427.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/momentum/apache/Config.lb
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@ -28,7 +28,7 @@ chip northbridge/ibm/cpc925
end end
end end
device pci 06.0 on end device pci 06.0 on end
chip southbridge/intel/ich5r # ich5r chip southbridge/intel/i82801er # i82801er
device pci 1d.0 on end device pci 1d.0 on end
device pci 1d.1 on end device pci 1d.1 on end
device pci 1d.2 on end device pci 1d.2 on end

2
src/mainboard/supermicro/x6dhe_g2/Config.lb
View File

@ -140,7 +140,7 @@ chip northbridge/intel/E7520 # MCH
device pnp 00.3 off end device pnp 00.3 off end
end end
device pci_domain 0 on device pci_domain 0 on
chip southbridge/intel/ich5r # ICH5R chip southbridge/intel/i82801er # ICH5R
register "pirq_a_d" = "0x0b070a05" register "pirq_a_d" = "0x0b070a05"
register "pirq_e_h" = "0x0a808080" register "pirq_e_h" = "0x0a808080"

2
src/mainboard/supermicro/x6dhe_g2/auto.c
View File

@ -10,7 +10,7 @@
#include "pc80/serial.c" #include "pc80/serial.c"
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#include "southbridge/intel/ich5r/ich5r_early_smbus.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/E7520/raminit.h" #include "northbridge/intel/E7520/raminit.h"
#include "superio/NSC/pc87427/pc87427.h" #include "superio/NSC/pc87427/pc87427.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/supermicro/x6dhr_ig/Config.lb
View File

@ -134,7 +134,7 @@ config chip.h
chip northbridge/intel/E7520 # mch chip northbridge/intel/E7520 # mch
device pci_domain 0 on device pci_domain 0 on
chip southbridge/intel/ich5r # ich5r chip southbridge/intel/i82801er # i82801er
# USB ports # USB ports
device pci 1d.0 on end device pci 1d.0 on end
device pci 1d.1 on end device pci 1d.1 on end

2
src/mainboard/supermicro/x6dhr_ig/auto.c
View File

@ -10,7 +10,7 @@
#include "pc80/serial.c" #include "pc80/serial.c"
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#include "southbridge/intel/ich5r/ich5r_early_smbus.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/E7520/raminit.h" #include "northbridge/intel/E7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h" #include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"

2
src/mainboard/supermicro/x6dhr_ig2/Config.lb
View File

@ -134,7 +134,7 @@ config chip.h
chip northbridge/intel/E7520 # mch chip northbridge/intel/E7520 # mch
device pci_domain 0 on device pci_domain 0 on
chip southbridge/intel/ich5r # ich5r chip southbridge/intel/i82801er # i82801er
# USB ports # USB ports
device pci 1d.0 on end device pci 1d.0 on end
device pci 1d.1 on end device pci 1d.1 on end

2
src/mainboard/supermicro/x6dhr_ig2/auto.c
View File

@ -10,7 +10,7 @@
#include "pc80/serial.c" #include "pc80/serial.c"
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#include "southbridge/intel/ich5r/ich5r_early_smbus.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/E7520/raminit.h" #include "northbridge/intel/E7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h" #include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"

11
src/southbridge/intel/i82801er/Config.lb
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@ -1,11 +0,0 @@
config chip.h
driver i82801er.o
driver i82801er_usb.o
driver i82801er_lpc.o
driver i82801er_ide.o
driver i82801er_sata.o
driver i82801er_usb2.o
driver i82801er_ac97.o
#driver i82801er_nic.o
#driver i82801er_pci.o
object i82801er_reset.o

9
src/southbridge/intel/i82801er/chip.h
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@ -1,9 +0,0 @@
#ifndef I82801ER_CHIP_H
#define I82801ER_CHIP_H
struct southbridge_intel_i82801er_config
{
};
extern struct chip_operations southbridge_intel_i82801er_ops;
#endif /* I82801ER_CHIP_H */

66
src/southbridge/intel/i82801er/i82801er.c
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@ -1,66 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801er.h"
void i82801er_enable(device_t dev)
{
unsigned int index = 0;
uint8_t bHasDisableBit = 0;
uint16_t cur_disable_mask, new_disable_mask;
// all 82801er devices are in bus 0
unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
device_t lpc_dev = dev_find_slot(0, devfn); // 0
if (!lpc_dev)
return;
// Calculate disable bit position for specified device:function
// NOTE: For ICH-5, only the following devices can be disabled:
// D31: F0, F1, F2, F3, F5, F6,
// D29: F0, F1, F2, F3, F7
if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
index = PCI_FUNC(dev->path.u.pci.devfn);
switch (index) {
case 0:
case 1:
case 2:
case 3:
case 5:
case 6:
bHasDisableBit = 1;
break;
default:
break;
};
if (index == 0)
index = 14; // D31:F0 bit is an exception
} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
if ((PCI_FUNC(dev->path.u.pci.devfn) < 4) || (PCI_FUNC(dev->path.u.pci.devfn) == 7))
bHasDisableBit = 1;
}
if (bHasDisableBit) {
cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
new_disable_mask = cur_disable_mask & ~(1<<index); // enable it
if (!dev->enabled) {
new_disable_mask |= (1<<index); // disable it
}
if (new_disable_mask != cur_disable_mask) {
pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
}
}
}
struct chip_operations southbridge_intel_i82801er_ops = {
CHIP_NAME("Intel 82801er Southbridge")
.enable_dev = i82801er_enable,
};

77
src/southbridge/intel/i82801er/i82801er.h
View File

@ -1,77 +0,0 @@
#ifndef I82801ER_H
#define I82801ER_H
#include "chip.h"
extern void i82801er_enable(device_t dev);
/*
000 = Non-combined. P0 is primary master. P1 is secondary master.
001 = Non-combined. P0 is secondary master. P1 is primary master.
100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel
disabled.
101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE
channel disabled.
111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
*/
#define ICH5_SATA_ADDRESS_MAP 0
#define PCI_DMA_CFG 0x90
#define SERIRQ_CNTL 0x64
#define GEN_CNTL 0xd0
#define GEN_STS 0xd4
#define RTC_CONF 0xd8
#define GEN_PMCON_3 0xa4
#define PCICMD 0x04
#define PMBASE 0x40
#define ACPI_CNTL 0x44
#define BIOS_CNTL 0x4E
#define GPIO_BASE 0x58
#define GPIO_CNTL 0x5C
#define PIRQA_ROUT 0x60
#define PIRQE_ROUT 0x68
#define COM_DEC 0xE0
#define LPC_EN 0xE6
#define FUNC_DIS 0xF2
/* 1e f0 244e */
#define CMD 0x04
#define SBUS_NUM 0x19
#define SUB_BUS_NUM 0x1A
#define SMLT 0x1B
#define IOBASE 0x1C
#define IOLIM 0x1D
#define MEMBASE 0x20
#define MEMLIM 0x22
#define CNF 0x50
#define MTT 0x70
#define PCI_MAST_STS 0x82
#define RTC_FAILED (1 <<2)
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0x0
#define SMBHSTCTL 0x2
#define SMBHSTCMD 0x3
#define SMBXMITADD 0x4
#define SMBHSTDAT0 0x5
#define SMBHSTDAT1 0x6
#define SMBBLKDAT 0x7
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
#define SMBUS_PIN_CTL 0xf
/* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs.
*/
#define SMBUS_TIMEOUT (100*1000)
#endif /* I82801ER_H */

41
src/southbridge/intel/i82801er/i82801er_ac97.c
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@ -1,41 +0,0 @@
/*
* (C) 2003 Linux Networx
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "i82801er.h"
static struct device_operations ac97audio_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable = i82801er_enable,
.init = 0,
.scan_bus = 0,
};
static struct pci_driver ac97audio_driver __pci_driver = {
.ops = &ac97audio_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1F5,
};
static struct device_operations ac97modem_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable = i82801er_enable,
.init = 0,
.scan_bus = 0,
};
static struct pci_driver ac97modem_driver __pci_driver = {
.ops = &ac97modem_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1F6,
};

175
src/southbridge/intel/i82801er/i82801er_early_smbus.c
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@ -1,175 +0,0 @@
//#define SMBUS_IO_BASE 0x1000
#define SMBUS_IO_BASE 0x0f00
#define SMBHSTSTAT 0x0
#define SMBHSTCTL 0x2
#define SMBHSTCMD 0x3
#define SMBXMITADD 0x4
#define SMBHSTDAT0 0x5
#define SMBHSTDAT1 0x6
#define SMBBLKDAT 0x7
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
#define SMBUS_PIN_CTL 0xf
/* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs.
*/
#define SMBUS_TIMEOUT (100*1000*10)
static void enable_smbus(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\r\n");
}
print_debug("SMBus controller enabled\r\n");
/* set smbus iobase */
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
/* Set smbus enable */
pci_write_config8(dev, 0x40, 0x01);
/* Set smbus iospace enable */
pci_write_config16(dev, 0x4, 0x01);
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
}
static inline void smbus_delay(void)
{
outb(0x80, 0x80);
}
static int smbus_wait_until_active(void)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
smbus_delay();
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
if ((val & 1)) {
break;
}
} while(--loops);
return loops?0:-4;
}
static int smbus_wait_until_ready(void)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
smbus_delay();
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
if ((val & 1) == 0) {
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
SMBUS_IO_BASE + SMBHSTSTAT);
}
} while(--loops);
return loops?0:-2;
}
static int smbus_wait_until_done(void)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
smbus_delay();
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
if ( (val & 1) == 0) {
break;
}
if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
break;
}
} while(--loops);
return loops?0:-3;
}
static int smbus_read_byte(unsigned device, unsigned address)
{
unsigned char global_control_register;
unsigned char global_status_register;
unsigned char byte;
if (smbus_wait_until_ready() < 0) {
return -2;
}
/* setup transaction */
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* clear the data byte...*/
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
/* start a byte read, with interrupts disabled */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
/* poll for it to start */
if (smbus_wait_until_active() < 0) {
return -4;
}
/* poll for transaction completion */
if (smbus_wait_until_done() < 0) {
return -3;
}
global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
/* read results of transaction */
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
if (global_status_register != 2) {
return -1;
}
return byte;
}
#if 0
static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
if (smbus_wait_until_ready() < 0) {
return;
}
/* by LYH */
outb(0x37,SMBUS_IO_BASE + SMBHSTSTAT);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
/* data to send */
outb(val, SMBUS_IO_BASE + SMBHSTDAT);
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* start the command */
outb(0xa, SMBUS_IO_BASE + SMBHSTCTL);
/* poll for transaction completion */
smbus_wait_until_done();
return;
}
#endif

53
src/southbridge/intel/i82801er/i82801er_ide.c
View File

@ -1,53 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "i82801er.h"
static void ide_init(struct device *dev)
{
#if ICH5_SATA_ADDRESS_MAP<=1
/* Enable ide devices so the linux ide driver will work */
uint16_t word;
uint8_t byte;
int enable_a=1, enable_b=1;
word = pci_read_config16(dev, 0x40);
word &= ~((1 << 15));
if (enable_a) {
/* Enable first ide interface */
word |= (1<<15);
printk_debug("IDE0 ");
}
pci_write_config16(dev, 0x40, word);
word = pci_read_config16(dev, 0x42);
word &= ~((1 << 15));
if (enable_b) {
/* Enable secondary ide interface */
word |= (1<<15);
printk_debug("IDE1 ");
}
pci_write_config16(dev, 0x42, word);
#endif
}
static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.scan_bus = 0,
.enable = i82801er_enable,
};
static struct pci_driver ide_driver __pci_driver = {
.ops = &ide_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1F1,
};

215
src/southbridge/intel/i82801er/i82801er_lpc.c
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@ -1,215 +0,0 @@
/*
* (C) 2003 Linux Networx, SuSE Linux AG
* (C) 2004 Tyan Computer
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
#include "i82801er.h"
#define NMI_OFF 0
void i82801er_enable_ioapic( struct device *dev)
{
uint32_t dword;
volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000;
volatile uint32_t *ioapic_sbd = (volatile uint32_t *)0xfec00010;
dword = pci_read_config32(dev, GEN_CNTL);
dword |= (3 << 7); /* enable ioapic */
dword |= (1 <<13); /* coprocessor error enable */
dword |= (1 << 1); /* delay transaction enable */
dword |= (1 << 2); /* DMA collection buf enable */
pci_write_config32(dev, GEN_CNTL, dword);
printk_debug("ioapic southbridge enabled %x\n",dword);
*ioapic_sba=0;
*ioapic_sbd=(2<<24);
//lyh *ioapic_sba=3;
//lyh *ioapic_sbd=1;
*ioapic_sba=0;
dword=*ioapic_sbd;
printk_debug("Southbridge apic id = %x\n",dword);
if(dword!=(2<<24))
for(;;);
//lyh *ioapic_sba=3;
//lyh dword=*ioapic_sbd;
//lyh printk_debug("Southbridge apic DT = %x\n",dword);
//lyh if(dword!=1)
//lyh for(;;);
}
void i82801er_enable_serial_irqs( struct device *dev)
{
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
}
void i82801er_lpc_route_dma( struct device *dev, uint8_t mask)
{
uint16_t word;
int i;
word = pci_read_config16(dev, PCI_DMA_CFG);
word &= ((1 << 10) - (1 << 8));
for(i = 0; i < 8; i++) {
if (i == 4)
continue;
word |= ((mask & (1 << i))? 3:1) << (i*2);
}
pci_write_config16(dev, PCI_DMA_CFG, word);
}
void i82801er_rtc_init(struct device *dev)
{
uint8_t byte;
uint32_t dword;
int rtc_failed;
byte = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = byte & RTC_FAILED;
if (rtc_failed) {
byte &= ~(1 << 1); /* preserve the power fail state */
pci_write_config8(dev, GEN_PMCON_3, byte);
}
dword = pci_read_config32(dev, GEN_STS);
rtc_failed |= dword & (1 << 2);
rtc_init(rtc_failed);
}
void i82801er_1f0_misc(struct device *dev)
{
pci_write_config16(dev, PCICMD, 0x014f);
pci_write_config32(dev, PMBASE, 0x00001001);
pci_write_config8(dev, ACPI_CNTL, 0x10);
pci_write_config32(dev, GPIO_BASE, 0x00001181);
pci_write_config8(dev, GPIO_CNTL, 0x10);
pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
pci_write_config8(dev, PIRQE_ROUT, 0x07);
pci_write_config8(dev, RTC_CONF, 0x04);
pci_write_config8(dev, COM_DEC, 0x10); //lyh E0->
pci_write_config16(dev, LPC_EN, 0x000F); //LYH 000D->
}
static void enable_hpet(struct device *dev)
{
const unsigned long hpet_address = 0xfed0000;
uint32_t dword;
uint32_t code = (0 & 0x3);
dword = pci_read_config32(dev, GEN_CNTL);
dword |= (1 << 17); /* enable hpet */
/*Bits [16:15]Memory Address Range
00 FED0_0000h - FED0_03FFh
01 FED0_1000h - FED0_13FFh
10 FED0_2000h - FED0_23FFh
11 FED0_3000h - FED0_33FFh*/
dword &= ~(3 << 15); /* clear it */
dword |= (code<<15);
printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) );
}
static void lpc_init(struct device *dev)
{
uint8_t byte;
int pwr_on=-1;
int nmi_option;
/* IO APIC initialization */
i82801er_enable_ioapic(dev);
i82801er_enable_serial_irqs(dev);
#ifdef SUSPICIOUS_LOOKING_CODE
// The ICH-5 datasheet does not mention this configuration register.
// This code may have been inherited (incorrectly) from code for the AMD 766 southbridge,
// which *does* support this functionality.
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
#endif
/* power after power fail */
/* FIXME this doesn't work! */
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
*/
pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1);
printk_info("set power %s after power fail\n", pwr_on?"on":"off");
#if 0
/* Enable Error reporting */
/* Set up sync flood detected */
byte = pci_read_config8(dev, 0x47);
byte |= (1 << 1);
pci_write_config8(dev, 0x47, byte);
#endif
/* Set up NMI on errors */
byte = inb(0x61);
byte &= ~(1 << 3); /* IOCHK# NMI Enable */
byte &= ~(1 << 2); /* PCI SERR# Enable */
outb(byte, 0x61);
byte = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
outb(byte, 0x70);
}
/* Initialize the real time clock */
i82801er_rtc_init(dev);
i82801er_lpc_route_dma(dev, 0xff);
/* Initialize isa dma */
isa_dma_init();
i82801er_1f0_misc(dev);
/* Initialize the High Precision Event Timers */
enable_hpet(dev);
}
static void i82801er_lpc_read_resources(device_t dev)
{
struct resource *res;
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void i82801er_lpc_enable_resources(device_t dev)
{
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static struct device_operations lpc_ops = {
.read_resources = i82801er_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = i82801er_lpc_enable_resources,
.init = lpc_init,
.scan_bus = scan_static_bus,
.enable = i82801er_enable,
};
static struct pci_driver lpc_driver __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1F0,
};

21
src/southbridge/intel/i82801er/i82801er_nic.c
View File

@ -1,21 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "i82801er.h"
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
};
static struct pci_driver nic_driver __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x1051,
};

33
src/southbridge/intel/i82801er/i82801er_pci.c
View File

@ -1,33 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "i82801er.h"
static void pci_init(struct device *dev)
{
/* Enable pci error detecting */
uint32_t dword;
/* System error enable */
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8); /* SERR# Enable */
dword |= (1<<6); /* Parity Error Response */
pci_write_config32(dev, 0x04, dword);
}
static struct device_operations pci_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pci_init,
.scan_bus = pci_scan_bridge,
};
static struct pci_driver pci_driver __pci_driver = {
.ops = &pci_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1E0,
};

75
src/southbridge/intel/i82801er/i82801er_sata.c
View File

@ -1,75 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "i82801er.h"
static void sata_init(struct device *dev)
{
uint16_t word;
uint8_t byte;
int enable_c=1, enable_d=1;
int i;
//Enable Serial ATA port
byte = pci_read_config8(dev,0x90);
byte &= 0xf8;
byte |= ICH5_SATA_ADDRESS_MAP & 7;
pci_write_config8(dev,0x90,byte);
// for(i=0;i<10;i++) {
word = pci_read_config16(dev,0x92);
word &= 0xfffc;
// if( (word & 0x0003) == 0x0003) break;
word |= 0x0003; // enable P0/P1
pci_write_config16(dev,0x92,word);
// }
// for(i=0;i<10;i++) {
/* enable ide0 */
word = pci_read_config16(dev, 0x40);
word &= ~(1 << 15);
if(enable_c==0) {
// if( (word & 0x8000) == 0x0000) break;
word |= 0x0000;
}
else {
// if( (word & 0x8000) == 0x8000) break;
word |= 0x8000;
}
pci_write_config16(dev, 0x40, word);
// }
/* enable ide1 */
// for(i=0;i<10;i++) {
word = pci_read_config16(dev, 0x42);
word &= ~(1 << 15);
if(enable_d==0) {
// if( (word & 0x8000) == 0x0000) break;
word |= 0x0000;
}
else {
// if( (word & 0x8000) == 0x8000) break;
word |= 0x8000;
}
pci_write_config16(dev, 0x42, word);
// }
}
static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sata_init,
.scan_bus = 0,
.enable = i82801er_enable,
};
static struct pci_driver stat_driver __pci_driver = {
.ops = &sata_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1F2_R,
};

92
src/southbridge/intel/i82801er/i82801er_smbus.c
View File

@ -1,92 +0,0 @@
#include <smbus.h>
#include <pci.h>
#include <arch/io.h>
#define PM_BUS 0
#define PM_DEVFN PCI_DEVFN(0x1f,3)
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
#define SMBHSTCMD 3
#define SMBHSTADD 4
#define SMBHSTDAT0 5
#define SMBHSTDAT1 6
#define SMBBLKDAT 7
void smbus_enable(void)
{
unsigned char byte;
/* iobase addr */
pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1);
/* smbus enable */
pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1);
/* iospace enable */
pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
}
void smbus_setup(void)
{
outb(0, SMBUS_IO_BASE + SMBHSTSTAT);
}
static void smbus_wait_until_ready(void)
{
while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
/* nop */
}
}
static void smbus_wait_until_done(void)
{
unsigned char byte;
do {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
while((byte &1) == 1);
while( (byte & ~1) == 0) {
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
}
int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
{
unsigned char host_status_register;
unsigned char byte;
smbus_wait_until_ready();
/* setup transaction */
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* clear the data byte...*/
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
/* start the command */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
/* poll for transaction completion */
smbus_wait_until_done();
host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
/* read results of transaction */
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
*result = byte;
return host_status_register != 0x02;
}

54
src/southbridge/intel/i82801er/i82801er_usb.c
View File

@ -1,54 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "i82801er.h"
static void usb_init(struct device *dev)
{
uint32_t cmd;
#if 0
printk_debug("USB: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
printk_debug("done.\n");
#endif
}
static struct device_operations usb_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = usb_init,
.scan_bus = 0,
.enable = i82801er_enable,
};
static struct pci_driver usb_driver_1 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1D0,
};
static struct pci_driver usb_driver_2 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1D1,
};
static struct pci_driver usb_driver_3 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1D2,
};
static struct pci_driver usb_driver_4 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1D3,
};

39
src/southbridge/intel/i82801er/i82801er_usb2.c
View File

@ -1,39 +0,0 @@
//2003 Copywright Tyan
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "i82801er.h"
static void usb2_init(struct device *dev)
{
uint32_t cmd;
#if 0
printk_debug("USB: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
printk_debug("done.\n");
#endif
}
static struct device_operations usb2_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = usb2_init,
.scan_bus = 0,
.enable = i82801er_enable,
};
static struct pci_driver usb2_driver __pci_driver = {
.ops = &usb2_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_1D7,
};

21
src/southbridge/intel/ich5r/Config.lb
View File

@ -1,11 +1,12 @@
config chip.h config chip.h
driver ich5r.o driver i82801er.o
driver ich5r_uhci.o driver i82801er_uhci.o
driver ich5r_lpc.o driver i82801er_lpc.o
driver ich5r_ide.o driver i82801er_ide.o
driver ich5r_sata.o driver i82801er_sata.o
driver ich5r_ehci.o driver i82801er_ehci.o
driver ich5r_smbus.o driver i82801er_smbus.o
driver ich5r_pci.o driver i82801er_pci.o
driver ich5r_ac97.o driver i82801er_ac97.o
object ich5r_watchdog.o object i82801er_watchdog.o
object i82801er_reset.o

10
src/southbridge/intel/ich5r/chip.h
View File

@ -1,4 +1,7 @@
struct southbridge_intel_ich5r_config #ifndef I82801ER_CHIP_H
#define I82801ER_CHIP_H
struct southbridge_intel_i82801er_config
{ {
#define ICH5R_GPIO_USE_MASK 0x03 #define ICH5R_GPIO_USE_MASK 0x03
@ -27,4 +30,7 @@ struct southbridge_intel_ich5r_config
unsigned int pirq_a_d; unsigned int pirq_a_d;
unsigned int pirq_e_h; unsigned int pirq_e_h;
}; };
extern struct chip_operations southbridge_intel_ich5r_ops; extern struct chip_operations southbridge_intel_i82801er_ops;
#endif /* I82801ER_CHIP_H */

0
src/southbridge/intel/i82801er/cmos_failover.c → src/southbridge/intel/ich5r/cmos_failover.c
View File

12
src/southbridge/intel/ich5r/ich5r.c → src/southbridge/intel/ich5r/i82801er.c
View File

@ -2,15 +2,15 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include "ich5r.h" #include "i82801er.h"
void ich5r_enable(device_t dev) void i82801er_enable(device_t dev)
{ {
device_t lpc_dev; device_t lpc_dev;
unsigned index = 0; unsigned index = 0;
uint16_t reg_old, reg; uint16_t reg_old, reg;
/* See if we are on the behind the ich5r pci bridge */ /* See if we are behind the i82801er pci bridge */
lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
if((dev->path.u.pci.devfn &0xf8)== 0xf8) { if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
index = dev->path.u.pci.devfn & 7; index = dev->path.u.pci.devfn & 7;
@ -42,7 +42,7 @@ void ich5r_enable(device_t dev)
} }
struct chip_operations southbridge_intel_ich5r_ops = { struct chip_operations southbridge_intel_i82801er_ops = {
CHIP_NAME("INTEL 82801ER") CHIP_NAME("Intel 82801ER Southbridge")
.enable_dev = ich5r_enable, .enable_dev = i82801er_enable,
}; };

15
src/southbridge/intel/ich5r/i82801er.h Normal file
View File

@ -0,0 +1,15 @@
#ifndef I82801ER_H
#define I82801ER_H
#include "chip.h"
extern void i82801er_enable(device_t dev);
#define PCI_DMA_CFG 0x90
#define SERIRQ_CNTL 0x64
#define GEN_CNTL 0xd0
#define GEN_STS 0xd4
#define RTC_CONF 0xd8
#define GEN_PMCON_3 0xa4
#endif /* I82801ER_H */

4
src/southbridge/intel/ich5r/ich5r_ac97.c → src/southbridge/intel/ich5r/i82801er_ac97.c
View File

@ -3,7 +3,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "ich5r.h" #include "i82801er.h"
static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{ {
@ -21,7 +21,7 @@ static struct device_operations ac97_ops = {
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = 0, .init = 0,
.scan_bus = 0, .scan_bus = 0,
.enable = ich5r_enable, .enable = i82801er_enable,
.ops_pci = &lops_pci, .ops_pci = &lops_pci,
}; };

14
src/southbridge/intel/ich5r/ich5r_early_smbus.c → src/southbridge/intel/ich5r/i82801er_early_smbus.c
View File

@ -1,4 +1,4 @@
#include "ich5r_smbus.h" #include "i82801er_smbus.h"
#define SMBUS_IO_BASE 0x0f00 #define SMBUS_IO_BASE 0x0f00
@ -9,10 +9,12 @@ static void enable_smbus(void)
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\r\n"); die("SMBUS controller not found\r\n");
} }
uint8_t enable;
print_spew("SMBus controller enabled\r\n"); print_spew("SMBus controller enabled\r\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
/* Set smbus enable */
pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x40, 1);
/* Set smbus iospace enable */
pci_write_config8(dev, 0x4, 1); pci_write_config8(dev, 0x4, 1);
/* SMBALERT_DIS */ /* SMBALERT_DIS */
pci_write_config8(dev, 0x11, 4); pci_write_config8(dev, 0x11, 4);
@ -20,10 +22,15 @@ static void enable_smbus(void)
/* Disable interrupt generation */ /* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL); outb(0, SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
#if 0 // It's unlikely that half the southbridge suddenly vanishes?
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
die("ISA bridge not found\r\n"); die("ISA bridge not found\r\n");
} }
#endif
} }
static int smbus_read_byte(unsigned device, unsigned address) static int smbus_read_byte(unsigned device, unsigned address)
@ -36,6 +43,9 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
return; return;
} }
print_debug("Unimplemented smbus_write_byte() called.\r\n");
#if 0 #if 0
/* setup transaction */ /* setup transaction */
/* disable interrupts */ /* disable interrupts */

4
src/southbridge/intel/ich5r/ich5r_ehci.c → src/southbridge/intel/ich5r/i82801er_ehci.c
View File

@ -3,7 +3,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "ich5r.h" #include "i82801er.h"
static void ehci_init(struct device *dev) static void ehci_init(struct device *dev)
{ {
@ -39,7 +39,7 @@ static struct device_operations ehci_ops = {
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = ehci_init, .init = ehci_init,
.scan_bus = 0, .scan_bus = 0,
.enable = ich5r_enable, .enable = i82801er_enable,
.ops_pci = &lops_pci, .ops_pci = &lops_pci,
}; };

11
src/southbridge/intel/ich5r/ich5r_ide.c → src/southbridge/intel/ich5r/i82801er_ide.c
View File

@ -3,21 +3,20 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "ich5r.h" #include "i82801er.h"
static void ide_init(struct device *dev) static void ide_init(struct device *dev)
{ {
/* Enable IDE devices and timmings */ /* Enable IDE devices and timmings */
pci_write_config16(dev, 0x40, 0x0a307); pci_write_config16(dev, 0x40, 0x0a307); // IDE0
pci_write_config16(dev, 0x42, 0x0a307); pci_write_config16(dev, 0x42, 0x0a307); // IDE1
pci_write_config8(dev, 0x48, 0x05); pci_write_config8(dev, 0x48, 0x05);
pci_write_config16(dev, 0x4a, 0x0101); pci_write_config16(dev, 0x4a, 0x0101);
pci_write_config16(dev, 0x54, 0x5055); pci_write_config16(dev, 0x54, 0x5055);
printk_debug("IDE Enabled\n"); printk_debug("IDE Enabled\n");
} }
static void ich5r_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void i82801er_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{ {
/* This value is also visible in uchi[0-2] and smbus functions */ /* This value is also visible in uchi[0-2] and smbus functions */
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@ -25,7 +24,7 @@ static void ich5r_ide_set_subsystem(device_t dev, unsigned vendor, unsigned devi
} }
static struct pci_operations lops_pci = { static struct pci_operations lops_pci = {
.set_subsystem = ich5r_ide_set_subsystem, .set_subsystem = i82801er_ide_set_subsystem,
}; };
static struct device_operations ide_ops = { static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,

73
src/southbridge/intel/ich5r/ich5r_lpc.c → src/southbridge/intel/ich5r/i82801er_lpc.c
View File

@ -9,7 +9,7 @@
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h> #include <pc80/isa-dma.h>
#include <arch/io.h> #include <arch/io.h>
#include "ich5r.h" #include "i82801er.h"
#define ACPI_BAR 0x40 #define ACPI_BAR 0x40
#define GPIO_BAR 0x58 #define GPIO_BAR 0x58
@ -68,7 +68,7 @@ static void setup_ioapic(void)
} }
#define SERIRQ_CNTL 0x64 #define SERIRQ_CNTL 0x64
static void ich5r_enable_serial_irqs(device_t dev) static void i82801er_enable_serial_irqs(device_t dev)
{ {
/* set packet length and toggle silent mode bit */ /* set packet length and toggle silent mode bit */
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
@ -76,22 +76,22 @@ static void ich5r_enable_serial_irqs(device_t dev)
} }
#define PCI_DMA_CFG 0x90 #define PCI_DMA_CFG 0x90
static void ich5r_pci_dma_cfg(device_t dev) static void i82801er_pci_dma_cfg(device_t dev)
{ {
/* Set PCI DMA CFG to lpc I/F DMA */ /* Set PCI DMA CFG to lpc I/F DMA */
pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); pci_write_config16(dev, PCI_DMA_CFG, 0xfcff);
} }
#define LPC_EN 0xe6 #define LPC_EN 0xe6
static void ich5r_enable_lpc(device_t dev) static void i82801er_enable_lpc(device_t dev)
{ {
/* lpc i/f enable */ /* lpc i/f enable */
pci_write_config8(dev, LPC_EN, 0x0d); pci_write_config8(dev, LPC_EN, 0x0d);
} }
typedef struct southbridge_intel_ich5r_config config_t; typedef struct southbridge_intel_i82801er_config config_t;
static void set_ich5r_gpio_use_sel( static void set_i82801er_gpio_use_sel(
device_t dev, struct resource *res, config_t *config) device_t dev, struct resource *res, config_t *config)
{ {
uint32_t gpio_use_sel, gpio_use_sel2; uint32_t gpio_use_sel, gpio_use_sel2;
@ -120,7 +120,7 @@ static void set_ich5r_gpio_use_sel(
outl(gpio_use_sel2, res->base + 0x30); outl(gpio_use_sel2, res->base + 0x30);
} }
static void set_ich5r_gpio_direction( static void set_i82801er_gpio_direction(
device_t dev, struct resource *res, config_t *config) device_t dev, struct resource *res, config_t *config)
{ {
uint32_t gpio_io_sel, gpio_io_sel2; uint32_t gpio_io_sel, gpio_io_sel2;
@ -149,7 +149,7 @@ static void set_ich5r_gpio_direction(
outl(gpio_io_sel2, res->base + 0x34); outl(gpio_io_sel2, res->base + 0x34);
} }
static void set_ich5r_gpio_level( static void set_i82801er_gpio_level(
device_t dev, struct resource *res, config_t *config) device_t dev, struct resource *res, config_t *config)
{ {
uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_lvl, gpio_lvl2;
@ -184,7 +184,7 @@ static void set_ich5r_gpio_level(
outl(gpio_lvl2, res->base + 0x38); outl(gpio_lvl2, res->base + 0x38);
} }
static void set_ich5r_gpio_inv( static void set_i82801er_gpio_inv(
device_t dev, struct resource *res, config_t *config) device_t dev, struct resource *res, config_t *config)
{ {
uint32_t gpio_inv; uint32_t gpio_inv;
@ -205,7 +205,7 @@ static void set_ich5r_gpio_inv(
outl(gpio_inv, res->base + 0x2c); outl(gpio_inv, res->base + 0x2c);
} }
static void ich5r_pirq_init(device_t dev) static void i82801er_pirq_init(device_t dev)
{ {
config_t *config; config_t *config;
@ -221,7 +221,7 @@ static void ich5r_pirq_init(device_t dev)
} }
static void ich5r_gpio_init(device_t dev) static void i82801er_gpio_init(device_t dev)
{ {
struct resource *res; struct resource *res;
config_t *config; config_t *config;
@ -243,19 +243,41 @@ static void ich5r_gpio_init(device_t dev)
} }
/* Set the use selects */ /* Set the use selects */
set_ich5r_gpio_use_sel(dev, res, config); set_i82801er_gpio_use_sel(dev, res, config);
/* Set the IO direction */ /* Set the IO direction */
set_ich5r_gpio_direction(dev, res, config); set_i82801er_gpio_direction(dev, res, config);
/* Setup the input inverters */ /* Setup the input inverters */
set_ich5r_gpio_inv(dev, res, config); set_i82801er_gpio_inv(dev, res, config);
/* Set the value on the GPIO output pins */ /* Set the value on the GPIO output pins */
set_ich5r_gpio_level(dev, res, config); set_i82801er_gpio_level(dev, res, config);
} }
static void enable_hpet(struct device *dev)
{
const unsigned long hpet_address = 0xfed0000;
uint32_t dword;
uint32_t code = (0 & 0x3);
dword = pci_read_config32(dev, GEN_CNTL);
dword |= (1 << 17); /* enable hpet */
/* Bits [16:15] Memory Address Range
* 00 FED0_0000h - FED0_03FFh
* 01 FED0_1000h - FED0_13FFh
* 10 FED0_2000h - FED0_23FFh
* 11 FED0_3000h - FED0_33FFh
*/
dword &= ~(3 << 15); /* clear it */
dword |= (code<<15);
printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) );
}
static void lpc_init(struct device *dev) static void lpc_init(struct device *dev)
{ {
@ -272,11 +294,11 @@ static void lpc_init(struct device *dev)
pci_write_config32(dev, 0xd4, value); pci_write_config32(dev, 0xd4, value);
setup_ioapic(); setup_ioapic();
ich5r_enable_serial_irqs(dev); i82801er_enable_serial_irqs(dev);
ich5r_pci_dma_cfg(dev); i82801er_pci_dma_cfg(dev);
ich5r_enable_lpc(dev); i82801er_enable_lpc(dev);
/* Clear SATA to non raid */ /* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00); pci_write_config8(dev, 0xae, 0x00);
@ -291,10 +313,10 @@ static void lpc_init(struct device *dev)
printk_info("set power %s after power fail\n", pwr_on?"on":"off"); printk_info("set power %s after power fail\n", pwr_on?"on":"off");
/* Set up the PIRQ */ /* Set up the PIRQ */
ich5r_pirq_init(dev); i82801er_pirq_init(dev);
/* Set the state of the gpio lines */ /* Set the state of the gpio lines */
ich5r_gpio_init(dev); i82801er_gpio_init(dev);
/* Initialize the real time clock */ /* Initialize the real time clock */
rtc_init(0); rtc_init(0);
@ -305,9 +327,10 @@ static void lpc_init(struct device *dev)
/* Disable IDE (needed when sata is enabled) */ /* Disable IDE (needed when sata is enabled) */
pci_write_config8(dev, 0xf2, 0x60); pci_write_config8(dev, 0xf2, 0x60);
enable_hpet(dev);
} }
static void ich5r_lpc_read_resources(device_t dev) static void i82801er_lpc_read_resources(device_t dev)
{ {
struct resource *res; struct resource *res;
@ -328,7 +351,7 @@ static void ich5r_lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
} }
static void ich5r_lpc_enable_resources(device_t dev) static void i82801er_lpc_enable_resources(device_t dev)
{ {
uint8_t acpi_cntl, gpio_cntl; uint8_t acpi_cntl, gpio_cntl;
@ -353,12 +376,12 @@ static struct pci_operations lops_pci = {
}; };
static struct device_operations lpc_ops = { static struct device_operations lpc_ops = {
.read_resources = ich5r_lpc_read_resources, .read_resources = i82801er_lpc_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = ich5r_lpc_enable_resources, .enable_resources = i82801er_lpc_enable_resources,
.init = lpc_init, .init = lpc_init,
.scan_bus = scan_static_bus, .scan_bus = scan_static_bus,
.enable = ich5r_enable, .enable = i82801er_enable,
.ops_pci = &lops_pci, .ops_pci = &lops_pci,
}; };

12
src/southbridge/intel/ich5r/ich5r_pci.c → src/southbridge/intel/ich5r/i82801er_pci.c
View File

@ -3,11 +3,11 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "ich5r.h" #include "i82801er.h"
static void pci_init(struct device *dev) static void pci_init(struct device *dev)
{ {
uint32_t dword;
uint16_t word; uint16_t word;
/* Clear system errors */ /* Clear system errors */
@ -15,6 +15,14 @@ static void pci_init(struct device *dev)
word |= 0xf900; /* Clear possible errors */ word |= 0xf900; /* Clear possible errors */
pci_write_config16(dev, 0x06, word); pci_write_config16(dev, 0x06, word);
#if 0
/* System error enable */
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8); /* SERR# Enable */
dword |= (1<<6); /* Parity Error Response */
pci_write_config32(dev, 0x04, dword);
#endif
word = pci_read_config16(dev, 0x1e); word = pci_read_config16(dev, 0x1e);
word |= 0xf800; /* Clear possible errors */ word |= 0xf800; /* Clear possible errors */
pci_write_config16(dev, 0x1e, word); pci_write_config16(dev, 0x1e, word);

0
src/southbridge/intel/i82801er/i82801er_reset.c → src/southbridge/intel/ich5r/i82801er_reset.c
View File

2
src/southbridge/intel/ich5r/ich5r_sata.c → src/southbridge/intel/ich5r/i82801er_sata.c
View File

@ -3,7 +3,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "ich5r.h" #include "i82801er.h"
static void sata_init(struct device *dev) static void sata_init(struct device *dev)
{ {

6
src/southbridge/intel/ich5r/ich5r_smbus.c → src/southbridge/intel/ich5r/i82801er_smbus.c
View File

@ -5,8 +5,8 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/smbus.h> #include <device/smbus.h>
#include <arch/io.h> #include <arch/io.h>
#include "ich5r.h" #include "i82801er.h"
#include "ich5r_smbus.h" #include "i82801er_smbus.h"
static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address) static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
{ {
@ -32,7 +32,7 @@ static struct device_operations smbus_ops = {
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = 0, .init = 0,
.scan_bus = scan_static_bus, .scan_bus = scan_static_bus,
.enable = ich5r_enable, .enable = i82801er_enable,
.ops_pci = &lops_pci, .ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus, .ops_smbus_bus = &lops_smbus_bus,
}; };

0
src/southbridge/intel/ich5r/ich5r_smbus.h → src/southbridge/intel/ich5r/i82801er_smbus.h
View File

4
src/southbridge/intel/ich5r/ich5r_uhci.c → src/southbridge/intel/ich5r/i82801er_uhci.c
View File

@ -3,7 +3,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "ich5r.h" #include "i82801er.h"
static void uhci_init(struct device *dev) static void uhci_init(struct device *dev)
{ {
@ -32,7 +32,7 @@ static struct device_operations uhci_ops = {
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = uhci_init, .init = uhci_init,
.scan_bus = 0, .scan_bus = 0,
.enable = ich5r_enable, .enable = i82801er_enable,
.ops_pci = &lops_pci, .ops_pci = &lops_pci,
}; };

0
src/southbridge/intel/ich5r/ich5r_watchdog.c → src/southbridge/intel/ich5r/i82801er_watchdog.c
View File

7
src/southbridge/intel/ich5r/ich5r.h
View File

@ -1,7 +0,0 @@
#ifndef ICH5R_H
#define ICH5R_H
#include "chip.h"
void ich5r_enable(device_t dev);
#endif /* ICH5R_H */