GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Prepare for next patches (Improving BKDG implementation of P-states, 

CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xA0,
Power Control Misc Register to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Xavi Drudis Ferran 2011-02-27 23:47:57 +00:00 committed by Marc Jones
parent a5cbd25e48
commit 9683b1deb2
1 changed files with 30 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
src/cpu/amd/model_10xxx/fidvid.c
View File

@ -231,9 +231,36 @@ static void config_clk_power_ctrl_reg0(int node) {
} }
} }
static void config_power_ctrl_misc_reg(device_t dev) {
/* check PVI/SVI */
u32 dword = pci_read_config32(dev, 0xA0);
if (dword & PVI_MODE) { /* PVI */
/* set slamVidMode to 0 for PVI */
dword &= VID_SLAM_OFF | PLLLOCK_OFF;
dword |= PLLLOCK_DFT_L;
pci_write_config32(dev, 0xA0, dword);
} else { /* SVI */
/* set slamVidMode to 1 for SVI */
dword &= PLLLOCK_OFF;
dword |= PLLLOCK_DFT_L | VID_SLAM_ON;
pci_write_config32(dev, 0xA0, dword);
u32 dtemp = dword;
/* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */
dword = pci_read_config32(dev, 0xD8);
if (dtemp & DUAL_VDD_BIT)
dword |= PWR_PLN_ON;
else
dword &= PWR_PLN_OFF;
pci_write_config32(dev, 0xD8, dword);
}
}
static void prep_fid_change(void) static void prep_fid_change(void)
{ {
u32 dword, dtemp; u32 dword;
u32 nodes; u32 nodes;
device_t dev; device_t dev;
int i; int i;
@ -253,31 +280,8 @@ static void prep_fid_change(void)
config_clk_power_ctrl_reg0(i); config_clk_power_ctrl_reg0(i);
/* check PVI/SVI */ config_power_ctrl_misc_reg(dev);
dword = pci_read_config32(dev, 0xA0);
if (dword & PVI_MODE) { /* PVI */
/* set slamVidMode to 0 for PVI */
dword &= VID_SLAM_OFF | PLLLOCK_OFF;
dword |= PLLLOCK_DFT_L;
pci_write_config32(dev, 0xA0, dword);
} else { /* SVI */
/* set slamVidMode to 1 for SVI */
dword &= PLLLOCK_OFF;
dword |= PLLLOCK_DFT_L | VID_SLAM_ON;
pci_write_config32(dev, 0xA0, dword);
dtemp = dword;
/* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */
dword = pci_read_config32(dev, 0xD8);
if (dtemp & DUAL_VDD_BIT)
dword |= PWR_PLN_ON;
else
dword &= PWR_PLN_OFF;
pci_write_config32(dev, 0xD8, dword);
}
/* Note the following settings are additional from the ported /* Note the following settings are additional from the ported
* function setFidVidRegs() * function setFidVidRegs()
*/ */