use hcdn to simplify the mptable.c and irqtable.c --- patch fro issue
48 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
parent
2c2d54479d
commit
968bbe89cd
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@ -814,12 +814,6 @@ define AGP_APERTURE_SIZE
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comment "AGP graphics virtual memory aperture size"
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end
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define CK804_DEVN_BASE
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default 1
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export always
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comment "CK804 device count from 0 or 1"
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end
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define HT_CHAIN_UNITID_BASE
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default 1
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export always
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@ -841,7 +835,7 @@ end
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define K8_SB_HT_CHAIN_ON_BUS0
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default 0
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export always
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comment "this will make SB hypertransport chain sit on bus 0"
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comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
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end
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define K8_HW_MEM_HOLE_SIZEK
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@ -53,6 +53,24 @@ if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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#if HAVE_ACPI_TABLES
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# object acpi_tables.o
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# object fadt.o
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# if K8_SB_HT_CHAIN_ON_BUS0
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# object dsdt_bus0.o
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# else
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# object dsdt.o
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# end
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# object ssdt.o
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# if ACPI_SSDTX_NUM
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# if K8_SB_HT_CHAIN_ON_BUS0
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# object ssdt2_bus0.o
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# else
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# object ssdt2.o
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# end
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# end
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#end
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if HAVE_ACPI_TABLES
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object acpi_tables.o
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object fadt.o
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@ -62,15 +80,14 @@ if HAVE_ACPI_TABLES
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action "/usr/sbin/iasl -tc $(MAINBOARD)/dx_bus0/dsdt_lb.dsl"
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action "mv dsdt_lb.hex dsdt.c"
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end
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object ./dsdt.o
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else
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makerule dsdt.c
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depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
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action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
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action "mv dsdt_lb.hex dsdt.c"
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end
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object ./dsdt.o
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end
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object ./dsdt.o
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makerule ssdt.c
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depends "$(MAINBOARD)/ssdt_lb_x.dsl"
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@ -88,7 +105,6 @@ if HAVE_ACPI_TABLES
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action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
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action "mv pci2.hex ssdt2.c"
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end
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object ./ssdt2.o
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else
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makerule ssdt2.c
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depends "$(MAINBOARD)/dx_bus0/pci2.asl"
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@ -96,9 +112,8 @@ if HAVE_ACPI_TABLES
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action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
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action "mv pci2.hex ssdt2.c"
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end
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object ./ssdt2.o
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end
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object ./ssdt2.o
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end
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end
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@ -48,45 +48,8 @@ unsigned hcdn[] =
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// 0x20202020,
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// 0x20202020,
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};
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static unsigned get_sbdn(void)
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{
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device_t dev;
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#if 0
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#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
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unsigned sbdn = 1 + HT_CHAIN_END_UNITID_BASE -1;
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#else
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unsigned sbdn = 3 + HT_CHAIN_UNITID_BASE - 1; // 8111 unit id base is 3 if 8131 before it
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#endif
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sbd3 = 1 + HT_CHAIN_UNITID_BASE - 1;
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#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
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sbd5 = 1;
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#else
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sbd5 = 1 + HT_CHAIN_UNITID_BASE - 1;
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#endif
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dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI , 0); //FIXME: if 8111 PCI is disabled?
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if(dev) {
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sbdn = (dev->path.u.pci.devfn >> 3) & 0x1f;
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}
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dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7458 , 0); //FIXME: if 8131 PCI is disabled?
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if(dev) {
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sbd3 = (dev->path.u.pci.devfn >> 3) & 0x1f;
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}
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dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7454 , 0); //FIXME: if 8151 PCI is disabled?
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if(dev) {
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sbd5 = (dev->path.u.pci.devfn >> 3) & 0x1f;
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}
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#endif
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sbdn = (hcdn[0] >> 8) & 0xff; // second byte
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return sbdn;
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}
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unsigned sbdn3;
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unsigned sbdn5;
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extern void get_sblk_pci1234(void);
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@ -107,7 +70,9 @@ void get_bus_conf(void)
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get_sblk_pci1234();
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sbdn = get_sbdn();
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sbdn = (hcdn[0] >> 8) & 0xff;
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sbdn3 = hcdn[0] & 0xff;
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sbdn5 = hcdn[1] & 0xff;
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// bus_8132_0 = node_link_to_bus(0, sblk);
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bus_8132_0 = (pci1234[0] >> 16) & 0xff;
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@ -128,7 +93,7 @@ void get_bus_conf(void)
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}
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/* 8132-1 */
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dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0]&0xff),0));
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dev = dev_find_slot(bus_8132_0, PCI_DEVFN(sbdn3,0));
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if (dev) {
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bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
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@ -142,7 +107,7 @@ void get_bus_conf(void)
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}
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/* 8132-2 */
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dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0] & 0xff)+1,0));
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dev = dev_find_slot(bus_8132_0, PCI_DEVFN(sbdn3+1,0));
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if (dev) {
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bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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@ -152,10 +117,9 @@ void get_bus_conf(void)
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/* HT chain 1 */
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if((pci1234[1] & 0x1) == 1) {
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// bus_8151_0 = node_link_to_bus( (pci1234[1]>>4) & 0xf, (pci1234[1]>>8) & 0xf);
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bus_8151_0 = (pci1234[1] >> 16) & 0xff;
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/* 8151 */
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dev = dev_find_slot(bus_8151_0, PCI_DEVFN((hcdn[1] & 0xff)+1, 0));
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dev = dev_find_slot(bus_8151_0, PCI_DEVFN(sbdn5+1, 0));
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if (dev) {
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bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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@ -10,33 +10,6 @@
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#include <stdint.h>
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*11, /* there can be total 11 devices on the bus */
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3, /* Where the interrupt router lies (bus) */
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(4<<3)|3, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x746b, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x42, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
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{0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
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{0x1,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
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{0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
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{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
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{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
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{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
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{0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
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{0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
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{0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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}
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};
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static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
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uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
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uint8_t slot, uint8_t rfu)
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@ -63,8 +36,12 @@ extern unsigned char bus_8111_1;
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extern unsigned char bus_8151_0;
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extern unsigned char bus_8151_1;
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extern unsigned pci1234[];
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extern unsigned sbdn;
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extern unsigned hcdn[];
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extern unsigned sbdn3;
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extern unsigned sbdn5;
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extern void get_bus_conf(void);
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@ -112,10 +89,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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pirq_info++; slot_num++;
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//pcix bridge
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// write_pirq_info(pirq_info, bus_8132_0, (sbd3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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// write_pirq_info(pirq_info, bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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// pirq_info++; slot_num++;
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if(pci1234[1] & 0xf) {
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//agp bridge
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write_pirq_info(pirq_info, bus_8151_0, ((hcdn[1] & 0xff)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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}
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pirq_info++; slot_num++;
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@ -19,8 +19,11 @@ extern unsigned apicid_8111;
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extern unsigned apicid_8132_1;
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extern unsigned apicid_8132_2;
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extern unsigned pci1234[];
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extern unsigned sbdn;
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extern unsigned hcdn[];
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extern unsigned sbdn3;
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extern unsigned sbdn5;
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extern void get_bus_conf(void);
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@ -32,6 +35,7 @@ void *smp_write_config_table(void *v)
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struct mp_config_table *mc;
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unsigned char bus_num;
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int i;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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@ -66,14 +70,14 @@ void *smp_write_config_table(void *v)
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{
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device_t dev;
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struct resource *res;
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dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0]&0xff), 1));
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dev = dev_find_slot(bus_8132_0, PCI_DEVFN(sbdn3, 1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, apicid_8132_1, 0x11, res->base);
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}
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}
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dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0]&0xff)+1, 1));
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dev = dev_find_slot(bus_8132_0, PCI_DEVFN(sbdn3+1, 1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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@ -103,32 +107,34 @@ void *smp_write_config_table(void *v)
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// Onboard AMD USB
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
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if(pci1234[1] & 0xf) {
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// Slot AGP
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x11);
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}
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//Slot 3 PCI 32
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|1, apicid_8111, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|2, apicid_8111, 0x13); //
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|3, apicid_8111, 0x10); //
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|i, apicid_8111, 0x10 + (1+i)%4); //16
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}
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//Slot 4 PCI 32
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|i, apicid_8111, 0x10 + (0+i)%4); //16
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}
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//Slot 1 PCI-X 133/100/66
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_2, (1<<2)|0, apicid_8132_2, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_2, (1<<2)|1, apicid_8132_2, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_2, (1<<2)|2, apicid_8132_2, 0x2); //
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_2, (1<<2)|3, apicid_8132_2, 0x3); //
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_2, (1<<2)|i, apicid_8132_2, (0+i)%4); //
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}
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//Slot 2 PCI-X 133/100/66
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_1, (1<<2)|0, apicid_8132_1, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_1, (1<<2)|1, apicid_8132_1, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_1, (1<<2)|2, apicid_8132_1, 0x3);//
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_1, (1<<2)|3, apicid_8132_1, 0x0);//
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8132_1, (1<<2)|i, apicid_8132_1, (1+i)%4); //25
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}
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
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@ -41,7 +41,7 @@ arch i386 end
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driver mainboard.o
|
||||
|
||||
#dir /drivers/si/3114
|
||||
|
||||
object get_bus_conf.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
object reset.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,123 @@
|
|||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
|
||||
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
||||
//busnum is default
|
||||
unsigned char bus_isa = 5 ;
|
||||
unsigned char bus_8131_0 = 1;
|
||||
unsigned char bus_8131_1 = 2;
|
||||
unsigned char bus_8131_2 = 3;
|
||||
unsigned char bus_8111_0 = 1;
|
||||
unsigned char bus_8111_1 = 4;
|
||||
unsigned apicid_8111 ;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
|
||||
unsigned sblk;
|
||||
unsigned pci1234[] =
|
||||
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0
|
||||
};
|
||||
unsigned hc_possible_num;
|
||||
unsigned sbdn;
|
||||
unsigned hcdn[] =
|
||||
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
|
||||
0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
};
|
||||
unsigned sbdn3;
|
||||
|
||||
extern void get_sblk_pci1234(void);
|
||||
|
||||
static unsigned get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
|
||||
unsigned apicid_base;
|
||||
|
||||
device_t dev;
|
||||
|
||||
if(get_bus_conf_done==1) return; //do it only once
|
||||
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sbdn = (hcdn[0] >> 8) & 0xff;
|
||||
sbdn3 = hcdn[0] & 0xff;
|
||||
|
||||
bus_8131_0 = (pci1234[0] >> 16) & 0xff;
|
||||
bus_8111_0 = bus_8131_0;
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0));
|
||||
if (dev) {
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
// printk_debug("bus_isa=%d\n",bus_isa);
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
// printk_debug("bus_isa=%d\n",bus_isa);
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
}
|
||||
|
||||
/* 8132-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
}
|
||||
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_8111 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
}
|
||||
|
|
@ -4,34 +4,104 @@
|
|||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*9, /* there can be total 9 devices on the bus */
|
||||
1, /* Where the interrupt router lies (bus) */
|
||||
(4<<3)|3, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1022, /* Vendor */
|
||||
0x746b, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x66, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
{1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x3,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x2,0x38, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x4, 0},
|
||||
{0x4,0x30, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x50, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x4,0x28, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
};
|
||||
|
||||
extern unsigned char bus_8131_0;
|
||||
extern unsigned char bus_8131_1;
|
||||
extern unsigned char bus_8131_2;
|
||||
extern unsigned char bus_8111_0;
|
||||
extern unsigned char bus_8111_1;
|
||||
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
unsigned slot_num;
|
||||
uint8_t *v;
|
||||
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *)(addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_8111_0;
|
||||
pirq->rtr_devfn = ((sbdn+1)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1022;
|
||||
pirq->rtr_device = 0x746b;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *) ( &pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
//pci bridge
|
||||
write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//pcix bridge
|
||||
// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
// pirq_info++; slot_num++;
|
||||
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk_info("done.\n");
|
||||
|
||||
return (unsigned long) pirq_info;
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,44 +3,24 @@
|
|||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
extern unsigned char bus_8131_0;
|
||||
extern unsigned char bus_8131_1;
|
||||
extern unsigned char bus_8131_2;
|
||||
extern unsigned char bus_8111_0;
|
||||
extern unsigned char bus_8111_1;
|
||||
extern unsigned apicid_8111;
|
||||
extern unsigned apicid_8131_1;
|
||||
extern unsigned apicid_8131_2;
|
||||
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned reg;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
uint32_t config_map;
|
||||
unsigned dst_node;
|
||||
unsigned dst_link;
|
||||
unsigned bus_base;
|
||||
config_map = pci_read_config32(dev, reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
dst_node = (config_map >> 4) & 7;
|
||||
dst_link = (config_map >> 8) & 3;
|
||||
bus_base = (config_map >> 16) & 0xff;
|
||||
#if 0
|
||||
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||
dst_node, dst_link, bus_base,
|
||||
reg, config_map);
|
||||
#endif
|
||||
if ((dst_node == node) && (dst_link == link))
|
||||
{
|
||||
return bus_base;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
|
|
@ -50,15 +30,8 @@ void *smp_write_config_table(void *v)
|
|||
struct mp_config_table *mc;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_chain_0;
|
||||
unsigned char bus_8131_1;
|
||||
unsigned char bus_8131_2;
|
||||
unsigned char bus_8111_1;
|
||||
unsigned apicid_base;
|
||||
unsigned apicid_8111;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
|
||||
int i;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
|
@ -79,53 +52,8 @@ void *smp_write_config_table(void *v)
|
|||
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* HT chain 0 */
|
||||
bus_chain_0 = node_link_to_bus(0, 2);
|
||||
if (bus_chain_0 == 0) {
|
||||
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||
bus_chain_0 = 1;
|
||||
}
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
|
||||
if (dev) {
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||
|
||||
bus_8111_1 = 4;
|
||||
bus_isa = 5;
|
||||
}
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
|
||||
|
||||
bus_8131_1 = 2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
|
||||
bus_8131_2 = 3;
|
||||
}
|
||||
}
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
|
|
@ -136,27 +64,18 @@ void *smp_write_config_table(void *v)
|
|||
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_8111 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
|
||||
smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
|
|
@ -166,8 +85,8 @@ void *smp_write_config_table(void *v)
|
|||
|
||||
}
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_8111, 0x3);
|
||||
|
|
@ -180,9 +99,8 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
|
||||
|
||||
/* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
|
||||
//8111 LPC ????
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|0, apicid_8111, 0x13);
|
||||
|
||||
//On Board AMD USB ???
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
|
||||
|
|
@ -194,29 +112,28 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
|
||||
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
|
||||
}
|
||||
|
||||
//On Board NIC and adaptec scsi
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, apicid_8131_1, 0x1);
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|i, apicid_8131_1, (0+i)%4); //24
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (0+i)%4); //24
|
||||
}
|
||||
|
||||
//Slot 1 PCI-X 133/100/66 or Side 1 on raiser card
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3);
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
|
||||
//Slot 1 PCI-X 133/100/66, Side 2 on raiser card
|
||||
//Fix ME, IRQ Pins?
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|0, apicid_8131_2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|1, apicid_8131_2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|2, apicid_8131_2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|3, apicid_8131_2, 0x0);
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (1+i)%4); //28
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ arch i386 end
|
|||
driver mainboard.o
|
||||
|
||||
#dir /drivers/si/3114
|
||||
|
||||
object get_bus_conf.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
object reset.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,139 @@
|
|||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
|
||||
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
||||
//busnum is default
|
||||
unsigned char bus_isa = 7 ;
|
||||
unsigned char bus_8131_0 = 1;
|
||||
unsigned char bus_8131_1 = 2;
|
||||
unsigned char bus_8131_2 = 3;
|
||||
unsigned char bus_8111_0 = 1;
|
||||
unsigned char bus_8111_1 = 4;
|
||||
unsigned char bus_8151_0 = 5;
|
||||
unsigned char bus_8151_1 = 6;
|
||||
unsigned apicid_8111 ;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
|
||||
unsigned sblk;
|
||||
unsigned pci1234[] =
|
||||
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
0x0000ff0,
|
||||
0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0
|
||||
};
|
||||
unsigned hc_possible_num;
|
||||
unsigned sbdn;
|
||||
unsigned hcdn[] =
|
||||
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
|
||||
0x20202020,
|
||||
0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
};
|
||||
unsigned sbdn3;
|
||||
unsigned sbdn5;
|
||||
|
||||
extern void get_sblk_pci1234(void);
|
||||
|
||||
static unsigned get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
|
||||
unsigned apicid_base;
|
||||
|
||||
device_t dev;
|
||||
|
||||
if(get_bus_conf_done==1) return; //do it only once
|
||||
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sbdn = (hcdn[0] >> 8) & 0xff;
|
||||
sbdn3 = hcdn[0] & 0xff;
|
||||
sbdn5 = hcdn[1] & 0xff;
|
||||
|
||||
bus_8131_0 = (pci1234[0] >> 16) & 0xff;
|
||||
bus_8111_0 = bus_8131_0;
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0));
|
||||
if (dev) {
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
// printk_debug("bus_isa=%d\n",bus_isa);
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
// printk_debug("bus_isa=%d\n",bus_isa);
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
}
|
||||
|
||||
/* 8132-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
}
|
||||
|
||||
/* HT chain 1 */
|
||||
// it is on node0, so it must be there
|
||||
bus_8151_0 = (pci1234[1] >> 16) & 0xff;
|
||||
/* 8151 */
|
||||
dev = dev_find_slot(bus_8151_0, PCI_DEVFN(sbdn5+1, 0));
|
||||
|
||||
if (dev) {
|
||||
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
// printk_debug("bus_8151_1=%d\n",bus_8151_1);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_8111 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
}
|
||||
|
|
@ -4,36 +4,109 @@
|
|||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*11, /* there can be total 11 devices on the bus */
|
||||
3, /* Where the interrupt router lies (bus) */
|
||||
(4<<3)|3, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1022, /* Vendor */
|
||||
0x746b, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x42, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
{3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x1,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
|
||||
{0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
};
|
||||
|
||||
extern unsigned char bus_8131_0;
|
||||
extern unsigned char bus_8131_1;
|
||||
extern unsigned char bus_8131_2;
|
||||
extern unsigned char bus_8111_0;
|
||||
extern unsigned char bus_8111_1;
|
||||
extern unsigned char bus_8151_0;
|
||||
extern unsigned char bus_8151_1;
|
||||
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
extern unsigned sbdn5;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
unsigned slot_num;
|
||||
uint8_t *v;
|
||||
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *)(addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_8111_0;
|
||||
pirq->rtr_devfn = ((sbdn+1)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1022;
|
||||
pirq->rtr_device = 0x746b;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *) ( &pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
//pci bridge
|
||||
write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//pcix bridge
|
||||
// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
// pirq_info++; slot_num++;
|
||||
//agp bridge
|
||||
write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk_info("done.\n");
|
||||
|
||||
return (unsigned long) pirq_info;
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,44 +3,25 @@
|
|||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
extern unsigned char bus_8131_0;
|
||||
extern unsigned char bus_8131_1;
|
||||
extern unsigned char bus_8131_2;
|
||||
extern unsigned char bus_8111_0;
|
||||
extern unsigned char bus_8111_1;
|
||||
extern unsigned char bus_8151_0;
|
||||
extern unsigned char bus_8151_1;
|
||||
extern unsigned apicid_8111;
|
||||
extern unsigned apicid_8131_1;
|
||||
extern unsigned apicid_8131_2;
|
||||
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned reg;
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
extern unsigned sbdn5;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
uint32_t config_map;
|
||||
unsigned dst_node;
|
||||
unsigned dst_link;
|
||||
unsigned bus_base;
|
||||
config_map = pci_read_config32(dev, reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
dst_node = (config_map >> 4) & 7;
|
||||
dst_link = (config_map >> 8) & 3;
|
||||
bus_base = (config_map >> 16) & 0xff;
|
||||
#if 0
|
||||
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||
dst_node, dst_link, bus_base,
|
||||
reg, config_map);
|
||||
#endif
|
||||
if ((dst_node == node) && (dst_link == link))
|
||||
{
|
||||
return bus_base;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
|
|
@ -51,18 +32,7 @@ void *smp_write_config_table(void *v)
|
|||
struct mp_config_table *mc;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_8131_0;
|
||||
unsigned char bus_8131_1;
|
||||
unsigned char bus_8131_2;
|
||||
unsigned char bus_8111_0;
|
||||
unsigned char bus_8111_1;
|
||||
unsigned char bus_8151_0;
|
||||
unsigned char bus_8151_1;
|
||||
unsigned apicid_base;
|
||||
unsigned apicid_8111;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
int i;
|
||||
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
|
@ -84,71 +54,7 @@ void *smp_write_config_table(void *v)
|
|||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* HT chain 0 */
|
||||
bus_8151_0 = node_link_to_bus(0, 0);
|
||||
if (bus_8151_0 == 0) {
|
||||
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||
bus_8151_0 = 1;
|
||||
}
|
||||
/* 8151 */
|
||||
dev = dev_find_slot(bus_8151_0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
// printk_debug("bus_8151_1=%d\n",bus_8151_1);
|
||||
bus_8111_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8111_0++;
|
||||
bus_8131_0 = bus_8111_0;
|
||||
// printk_debug("bus_8111_0=%d\n",bus_8111_0);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
bus_8151_1 = 2;
|
||||
bus_8111_0 = bus_8131_0 = 3;
|
||||
}
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(0x03,0));
|
||||
if (dev) {
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
// printk_debug("bus_isa=%d\n",bus_isa);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
|
||||
|
||||
bus_8111_1 = 6;
|
||||
bus_isa = 7;
|
||||
}
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_1 = 4;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_2 = 5;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
|
|
@ -158,26 +64,18 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_8111 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); //8111
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x1,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x2,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
|
|
@ -201,9 +99,9 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
|
||||
//??? What
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (4<<2)|3, apicid_8111, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|3, apicid_8111, 0x13);
|
||||
//Onboard AMD AC97 Audio
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (4<<2)|1, apicid_8111, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|1, apicid_8111, 0x11);
|
||||
// Onboard AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
|
||||
|
||||
|
|
@ -218,34 +116,33 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
|
||||
|
||||
//Slot 5 PCI 32
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, apicid_8111, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, apicid_8111, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, apicid_8111, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, apicid_8111, 0x13); //
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|i, apicid_8111, 0x10 + (0+i)%4); //16
|
||||
}
|
||||
|
||||
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);//
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
|
||||
}
|
||||
|
||||
|
||||
//Slot 4 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, apicid_8131_1, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, apicid_8131_1, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, apicid_8131_1, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|3, apicid_8131_1, 0x1);//
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26
|
||||
}
|
||||
|
||||
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
|
||||
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, apicid_8131_2, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, apicid_8131_2, 0x0);//
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (1+i)%4); //29
|
||||
}
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
|||
|
|
@ -44,6 +44,9 @@ driver mainboard.o
|
|||
|
||||
#dir /drivers/ati/ragexl
|
||||
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
object get_bus_conf.o
|
||||
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#object reset.o
|
||||
|
|
|
|||
|
|
@ -55,8 +55,6 @@ uses CONFIG_CONSOLE_VGA
|
|||
uses CONFIG_PCI_ROM_RUN
|
||||
uses K8_HW_MEM_HOLE_SIZEK
|
||||
|
||||
uses CK804_DEVN_BASE
|
||||
|
||||
uses USE_DCACHE_RAM
|
||||
uses DCACHE_RAM_BASE
|
||||
uses DCACHE_RAM_SIZE
|
||||
|
|
@ -133,10 +131,6 @@ default CONFIG_LOGICAL_CPUS=1
|
|||
#1G memory hole
|
||||
default K8_HW_MEM_HOLE_SIZEK=0x100000
|
||||
|
||||
#CK804 setting
|
||||
|
||||
default CK804_DEVN_BASE=0
|
||||
|
||||
#BTEXT Console
|
||||
#default CONFIG_CONSOLE_BTEXT=1
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,196 @@
|
|||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
|
||||
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
||||
//busnum is default
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_ck804_0; //1
|
||||
unsigned char bus_ck804_1; //2
|
||||
unsigned char bus_ck804_2; //3
|
||||
unsigned char bus_ck804_3; //4
|
||||
unsigned char bus_ck804_4; //5
|
||||
unsigned char bus_ck804_5; //6
|
||||
unsigned char bus_8131_0; //7
|
||||
unsigned char bus_8131_1; //8
|
||||
unsigned char bus_8131_2; //9
|
||||
unsigned apicid_ck804;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
|
||||
unsigned sblk;
|
||||
unsigned pci1234[] =
|
||||
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
0x0000ff0,
|
||||
0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0
|
||||
};
|
||||
unsigned hc_possible_num;
|
||||
unsigned sbdn;
|
||||
unsigned hcdn[] =
|
||||
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
|
||||
0x20202020,
|
||||
0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
};
|
||||
|
||||
unsigned sbdn3;
|
||||
|
||||
extern void get_sblk_pci1234(void);
|
||||
|
||||
static unsigned get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
|
||||
unsigned apicid_base;
|
||||
|
||||
device_t dev;
|
||||
|
||||
if(get_bus_conf_done==1) return; //do it only once
|
||||
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sbdn = (hcdn[0] & 0xff); // first byte of first chain
|
||||
|
||||
sbdn3 = (hcdn[1] & 0xff); // first byte of second chain
|
||||
|
||||
// bus_ck804_0 = node_link_to_bus(0, sblk);
|
||||
bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
|
||||
|
||||
|
||||
/* CK804 */
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_4 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_0++;
|
||||
bus_isa = bus_8131_0; // incase only one installed
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
|
||||
|
||||
bus_8131_0 = bus_ck804_5+1;
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_1 = bus_8131_0+1;
|
||||
bus_8131_2 = bus_8131_0+2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_2 = bus_8131_1+1;
|
||||
bus_isa = bus_8131_1+2;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_ck804 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
}
|
||||
|
|
@ -10,71 +10,6 @@
|
|||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*11, /* there can be total 11 devices on the bus */
|
||||
1, /* Where the interrupt router lies (bus) */
|
||||
((CK804_DEVN_BASE+9)<<3)|0, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x10de, /* Vendor */
|
||||
0x005c, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
#if CK804_DEVN_BASE==0
|
||||
0x31, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
#else
|
||||
0x19,
|
||||
#endif
|
||||
{
|
||||
{1,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x4,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x7,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x0, 0},
|
||||
{0x8,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
}
|
||||
};
|
||||
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned reg;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
uint32_t config_map;
|
||||
unsigned dst_node;
|
||||
unsigned dst_link;
|
||||
unsigned bus_base;
|
||||
config_map = pci_read_config32(dev, reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
dst_node = (config_map >> 4) & 7;
|
||||
dst_link = (config_map >> 8) & 3;
|
||||
bus_base = (config_map >> 16) & 0xff;
|
||||
#if 0
|
||||
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||
dst_node, dst_link, bus_base,
|
||||
reg, config_map);
|
||||
#endif
|
||||
if ((dst_node == node) && (dst_link == link))
|
||||
{
|
||||
return bus_base;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
|
|
@ -93,6 +28,23 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
|
|||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
extern unsigned char bus_ck804_0; //1
|
||||
extern unsigned char bus_ck804_1; //2
|
||||
extern unsigned char bus_ck804_2; //3
|
||||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0;//7
|
||||
extern unsigned char bus_8131_1;//8
|
||||
extern unsigned char bus_8131_2;//9
|
||||
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
|
|
@ -104,126 +56,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
uint8_t sum=0;
|
||||
int i;
|
||||
|
||||
unsigned char bus_ck804_0; //1
|
||||
unsigned char bus_ck804_1; //2
|
||||
unsigned char bus_ck804_2; //3
|
||||
unsigned char bus_ck804_3; //4
|
||||
unsigned char bus_ck804_4; //5
|
||||
unsigned char bus_ck804_5; //6
|
||||
unsigned char bus_8131_0; //7
|
||||
unsigned char bus_8131_1; //8
|
||||
unsigned char bus_8131_2; //9
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
|
||||
bus_ck804_0 = node_link_to_bus(0, 0);
|
||||
if (bus_ck804_0 == 0) {
|
||||
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||
bus_ck804_0 = 1;
|
||||
}
|
||||
/* CK804 */
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_4 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_0++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0e);
|
||||
|
||||
bus_8131_0 = bus_ck804_5+1;
|
||||
}
|
||||
|
||||
bus_8131_0 = node_link_to_bus(0, 2);
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_1 = bus_8131_0+1;
|
||||
bus_8131_2 = bus_8131_0+2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_2 = bus_8131_1+1;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
|
|
@ -239,7 +72,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_ck804_0;
|
||||
pirq->rtr_devfn = ((CK804_DEVN_BASE+9)<<3)|0;
|
||||
pirq->rtr_devfn = ((sbdn+9)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
|
|
@ -253,32 +86,32 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
pirq_info = (void *) ( &pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
//pci bridge
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//pcix bridge
|
||||
write_pirq_info(pirq_info, bus_8131_0, (1<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
#if 0
|
||||
//smbus
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//usb
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//audio
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot1 PCIE x16
|
||||
|
|
@ -292,9 +125,6 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
//Slot2 pci
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804b_0, ((CK804_DEVN_BASE+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//Slot3 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
|
@ -307,10 +137,6 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//onboard scsi
|
||||
write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot6 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
|
|
|||
|
|
@ -3,44 +3,26 @@
|
|||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
extern unsigned char bus_ck804_0; //1
|
||||
extern unsigned char bus_ck804_1; //2
|
||||
extern unsigned char bus_ck804_2; //3
|
||||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0;//7
|
||||
extern unsigned char bus_8131_1;//8
|
||||
extern unsigned char bus_8131_2;//9
|
||||
extern unsigned apicid_ck804;
|
||||
extern unsigned apicid_8131_1;
|
||||
extern unsigned apicid_8131_2;
|
||||
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned reg;
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
uint32_t config_map;
|
||||
unsigned dst_node;
|
||||
unsigned dst_link;
|
||||
unsigned bus_base;
|
||||
config_map = pci_read_config32(dev, reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
dst_node = (config_map >> 4) & 7;
|
||||
dst_link = (config_map >> 8) & 3;
|
||||
bus_base = (config_map >> 16) & 0xff;
|
||||
#if 0
|
||||
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||
dst_node, dst_link, bus_base,
|
||||
reg, config_map);
|
||||
#endif
|
||||
if ((dst_node == node) && (dst_link == link))
|
||||
{
|
||||
return bus_base;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
|
|
@ -50,20 +32,7 @@ void *smp_write_config_table(void *v)
|
|||
struct mp_config_table *mc;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_ck804_0; //1
|
||||
unsigned char bus_ck804_1; //2
|
||||
unsigned char bus_ck804_2; //3
|
||||
unsigned char bus_ck804_3; //4
|
||||
unsigned char bus_ck804_4; //5
|
||||
unsigned char bus_ck804_5; //6
|
||||
unsigned char bus_8131_0; //7
|
||||
unsigned char bus_8131_1; //8
|
||||
unsigned char bus_8131_2; //9
|
||||
unsigned apicid_base;
|
||||
unsigned apicid_ck804;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
int i;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
|
@ -84,117 +53,7 @@ void *smp_write_config_table(void *v)
|
|||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
bus_ck804_0 = node_link_to_bus(0, 0);
|
||||
if (bus_ck804_0 == 0) {
|
||||
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||
bus_ck804_0 = 1;
|
||||
}
|
||||
|
||||
/* CK804 */
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_4 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
#endif
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_0++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0e);
|
||||
|
||||
bus_8131_0 = bus_ck804_5+1;
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_1 = bus_8131_0+1;
|
||||
bus_8131_2 = bus_8131_0+2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_2 = bus_8131_1+1;
|
||||
bus_isa = bus_8131_1+2;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
|
|
@ -204,21 +63,12 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_ck804 = apicid_base;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
// smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
uint32_t dword;
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE+ 0x1,0));
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
|
|
@ -233,18 +83,19 @@ void *smp_write_config_table(void *v)
|
|||
pci_write_config32(dev, 0x80, dword);
|
||||
|
||||
dword = 0x0000007d;
|
||||
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x1,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x2,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
|
|
@ -268,56 +119,54 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_ck804, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa);
|
||||
// Onboard ck804 smbus
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
|
||||
// 10
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
// Onboard ck804 USB 1.1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
// Onboard ck804 USB 2
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
// Onboard ck804 SATA 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
// Onboard ck804 SATA 1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
|
||||
#if CK804_DEVN_BASE == 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); //
|
||||
#else
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); //
|
||||
#endif
|
||||
//Slot PCIE x16
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
#if CK804_DEVN_BASE == 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // 17
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x10); //
|
||||
#else
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x10); // 16
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x11); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x13); //
|
||||
#endif
|
||||
//Slot PCIE x4
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
//Onboard ati
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0); //24+4+0 = 28
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x1);
|
||||
//Channel B of 8131
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x0); // 24
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x2);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x3);//
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x2); // 26
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, apicid_8131_1, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|2, apicid_8131_1, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|3, apicid_8131_1, 0x1);//
|
||||
//Onboard Broadcom NIC
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
|
||||
//Channel A of 8131
|
||||
|
||||
//Slot 4 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24
|
||||
}
|
||||
|
||||
//Slot 3 PCIX 133/100/66 SoDIMM PCI
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26
|
||||
}
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
|||
|
|
@ -43,6 +43,9 @@ arch i386 end
|
|||
driver mainboard.o
|
||||
|
||||
#dir /drivers/ati/ragexl
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
object get_bus_conf.o
|
||||
|
||||
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
|
|
|
|||
|
|
@ -55,8 +55,6 @@ uses CONFIG_CONSOLE_VGA
|
|||
uses CONFIG_PCI_ROM_RUN
|
||||
uses K8_HW_MEM_HOLE_SIZEK
|
||||
|
||||
uses CK804_DEVN_BASE
|
||||
|
||||
uses USE_DCACHE_RAM
|
||||
uses DCACHE_RAM_BASE
|
||||
uses DCACHE_RAM_SIZE
|
||||
|
|
@ -127,10 +125,6 @@ default CONFIG_LOGICAL_CPUS=1
|
|||
#1G memory hole
|
||||
default K8_HW_MEM_HOLE_SIZEK=0x100000
|
||||
|
||||
#CK804 setting
|
||||
|
||||
default CK804_DEVN_BASE=0
|
||||
|
||||
#BTEXT Console
|
||||
#default CONFIG_CONSOLE_BTEXT=1
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,196 @@
|
|||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
|
||||
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
||||
//busnum is default
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_ck804_0; //1
|
||||
unsigned char bus_ck804_1; //2
|
||||
unsigned char bus_ck804_2; //3
|
||||
unsigned char bus_ck804_3; //4
|
||||
unsigned char bus_ck804_4; //5
|
||||
unsigned char bus_ck804_5; //6
|
||||
unsigned char bus_8131_0; //7
|
||||
unsigned char bus_8131_1; //8
|
||||
unsigned char bus_8131_2; //9
|
||||
unsigned apicid_ck804;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
|
||||
unsigned sblk;
|
||||
unsigned pci1234[] =
|
||||
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
0x0000ff0,
|
||||
0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0
|
||||
};
|
||||
unsigned hc_possible_num;
|
||||
unsigned sbdn;
|
||||
unsigned hcdn[] =
|
||||
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
|
||||
0x20202020,
|
||||
0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
};
|
||||
|
||||
unsigned sbdn3;
|
||||
|
||||
extern void get_sblk_pci1234(void);
|
||||
|
||||
static unsigned get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
|
||||
unsigned apicid_base;
|
||||
|
||||
device_t dev;
|
||||
|
||||
if(get_bus_conf_done==1) return; //do it only once
|
||||
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sbdn = (hcdn[0] & 0xff); // first byte of first chain
|
||||
|
||||
sbdn3 = (hcdn[1] & 0xff); // first byte of second chain
|
||||
|
||||
// bus_ck804_0 = node_link_to_bus(0, sblk);
|
||||
bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
|
||||
|
||||
|
||||
/* CK804 */
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_4 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_0++;
|
||||
bus_isa = bus_8131_0; // incase only one installed
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
|
||||
|
||||
bus_8131_0 = bus_ck804_5+1;
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_1 = bus_8131_0+1;
|
||||
bus_8131_2 = bus_8131_0+2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_2 = bus_8131_1+1;
|
||||
bus_isa = bus_8131_1+2;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_ck804 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
}
|
||||
|
|
@ -4,36 +4,157 @@
|
|||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*11, /* there can be total 11 devices on the bus */
|
||||
1, /* Where the interrupt router lies (bus) */
|
||||
((CK804_DEVN_BASE+9)<<3)|0, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x10de, /* Vendor */
|
||||
0x005c, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x5a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
{1,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x5,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x5,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x0, 0},
|
||||
{0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
};
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
extern unsigned char bus_ck804_0; //1
|
||||
extern unsigned char bus_ck804_1; //2
|
||||
extern unsigned char bus_ck804_2; //3
|
||||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0;//7
|
||||
extern unsigned char bus_8131_1;//8
|
||||
extern unsigned char bus_8131_2;//9
|
||||
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
unsigned slot_num;
|
||||
uint8_t *v;
|
||||
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *)(addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_ck804_0;
|
||||
pirq->rtr_devfn = ((sbdn+9)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x10de;
|
||||
pirq->rtr_device = 0x005c;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *) ( &pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
//pci bridge
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//pcix bridge
|
||||
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
#if 0
|
||||
//smbus
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//usb
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//audio
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot1 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//firewire
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot2 pci
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//Slot3 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot4 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot5 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot6 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
|
||||
pirq_info++; slot_num++;
|
||||
#endif
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk_info("done.\n");
|
||||
|
||||
return (unsigned long) pirq_info;
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,44 +3,25 @@
|
|||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
extern unsigned char bus_ck804_0; //1
|
||||
extern unsigned char bus_ck804_1; //2
|
||||
extern unsigned char bus_ck804_2; //3
|
||||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0;//7
|
||||
extern unsigned char bus_8131_1;//8
|
||||
extern unsigned char bus_8131_2;//9
|
||||
extern unsigned apicid_ck804;
|
||||
extern unsigned apicid_8131_1;
|
||||
extern unsigned apicid_8131_2;
|
||||
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned reg;
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
uint32_t config_map;
|
||||
unsigned dst_node;
|
||||
unsigned dst_link;
|
||||
unsigned bus_base;
|
||||
config_map = pci_read_config32(dev, reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
dst_node = (config_map >> 4) & 7;
|
||||
dst_link = (config_map >> 8) & 3;
|
||||
bus_base = (config_map >> 16) & 0xff;
|
||||
#if 0
|
||||
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||
dst_node, dst_link, bus_base,
|
||||
reg, config_map);
|
||||
#endif
|
||||
if ((dst_node == node) && (dst_link == link))
|
||||
{
|
||||
return bus_base;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
|
|
@ -50,20 +31,7 @@ void *smp_write_config_table(void *v)
|
|||
struct mp_config_table *mc;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_ck804_0; //1
|
||||
unsigned char bus_ck804_1; //2
|
||||
unsigned char bus_ck804_2; //3
|
||||
unsigned char bus_ck804_3; //4
|
||||
unsigned char bus_ck804_4; //5
|
||||
unsigned char bus_ck804_5; //6
|
||||
unsigned char bus_8131_0; //7
|
||||
unsigned char bus_8131_1; //8
|
||||
unsigned char bus_8131_2; //9
|
||||
unsigned apicid_base;
|
||||
unsigned apicid_ck804;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
int i;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
|
@ -84,117 +52,7 @@ void *smp_write_config_table(void *v)
|
|||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
bus_ck804_0 = node_link_to_bus(0, 0);
|
||||
if (bus_ck804_0 == 0) {
|
||||
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||
bus_ck804_0 = 1;
|
||||
}
|
||||
|
||||
/* CK804 */
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_4 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
#endif
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_0++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0e);
|
||||
|
||||
bus_8131_0 = bus_ck804_5+1;
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_1 = bus_8131_0+1;
|
||||
bus_8131_2 = bus_8131_0+2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_2 = bus_8131_1+1;
|
||||
bus_isa = bus_8131_1+2;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
|
|
@ -204,33 +62,23 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_ck804 = apicid_base;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
// smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
uint32_t dword;
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE+ 0x1,0));
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
|
||||
}
|
||||
|
||||
/* Initialize interrupt mapping*/
|
||||
|
||||
dword = 0x0000d218;
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
|
||||
dword = 0x12008a00;
|
||||
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
|
||||
dword = 0x0000007d;
|
||||
|
|
@ -238,14 +86,14 @@ void *smp_write_config_table(void *v)
|
|||
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x1,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x2,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
|
|
@ -269,79 +117,76 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_ck804, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa);
|
||||
// Onboard ck804 smbus
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
|
||||
// 10
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
// Onboard ck804 USB 1.1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
// Onboard ck804 USB 2
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
// Onboard ck804 SATA 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
// Onboard ck804 SATA 1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
|
||||
#if CK804_DEVN_BASE == 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); //
|
||||
#else
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); //
|
||||
#endif
|
||||
//Slot PCIE x16
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
#if CK804_DEVN_BASE == 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x11); // 17
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x10); //
|
||||
#else
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|0, apicid_ck804, 0x10); // 16
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|1, apicid_ck804, 0x11); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|2, apicid_ck804, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|3, apicid_ck804, 0x13); //
|
||||
#endif
|
||||
//Slot PCIE x4
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // 16
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // 17
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // 18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // 19
|
||||
//Slot 2 PCI 32
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (4<<2)|i, apicid_ck804, 0x10+(0+i)%4); //16
|
||||
}
|
||||
|
||||
|
||||
//Onboard ati
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // 18
|
||||
|
||||
//Onboard intel 10/100
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // 18
|
||||
|
||||
//Channel B of 8131
|
||||
|
||||
|
||||
//Onboard Broadcom NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x0);//24+4= 28
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x1);
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
|
||||
//SO DIMM PCI-X
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|0, apicid_8131_2, 0x0);//28
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|1, apicid_8131_2, 0x1);
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
|
||||
//Slot 4 PCIX 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x2); // 30
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x0);// 28
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x1);//
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (2+i)%4); //30
|
||||
}
|
||||
|
||||
|
||||
//Channel A of 8131
|
||||
|
||||
//Slot 5 PCIX 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); //28
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);//24
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|i, apicid_8131_1, (3+i)%4); //27
|
||||
}
|
||||
|
||||
|
||||
//Slot 6 PCIX 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); // 27
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// 24
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|i, apicid_8131_1, (2+i)%4); //26
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
|
|
|
|||
|
|
@ -41,6 +41,9 @@ arch i386 end
|
|||
##
|
||||
|
||||
driver mainboard.o
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
object get_bus_conf.o
|
||||
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#object reset.o
|
||||
|
|
|
|||
|
|
@ -55,8 +55,6 @@ uses CONFIG_PCI_ROM_RUN
|
|||
uses K8_HW_MEM_HOLE_SIZEK
|
||||
uses K8_HT_FREQ_1G_SUPPORT
|
||||
|
||||
uses CK804_DEVN_BASE
|
||||
|
||||
uses USE_DCACHE_RAM
|
||||
uses DCACHE_RAM_BASE
|
||||
uses DCACHE_RAM_SIZE
|
||||
|
|
@ -136,9 +134,6 @@ default K8_HW_MEM_HOLE_SIZEK=0x100000
|
|||
#Opteron K8 1G HT Support
|
||||
default K8_HT_FREQ_1G_SUPPORT=1
|
||||
|
||||
#CK804 setting
|
||||
#default CK804_DEVN_BASE=0
|
||||
|
||||
#VGA
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
|
|
|||
|
|
@ -113,7 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
|
||||
#define CK804_NUM 2
|
||||
#define CK804B_BUSN 0x80
|
||||
#define CK804_USE_NIC 1
|
||||
#define CK804_USE_ACI 1
|
||||
|
||||
|
|
@ -128,7 +127,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
|
||||
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
|
||||
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,271 @@
|
|||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
|
||||
|
||||
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
||||
//busnum is default
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_ck804_0; //1
|
||||
unsigned char bus_ck804_1; //2
|
||||
unsigned char bus_ck804_2; //3
|
||||
unsigned char bus_ck804_3; //4
|
||||
unsigned char bus_ck804_4; //5
|
||||
unsigned char bus_ck804_5; //6
|
||||
unsigned char bus_8131_0; //7
|
||||
unsigned char bus_8131_1; //8
|
||||
unsigned char bus_8131_2; //9
|
||||
unsigned char bus_ck804b_0;//a
|
||||
unsigned char bus_ck804b_1;//b
|
||||
unsigned char bus_ck804b_2;//c
|
||||
unsigned char bus_ck804b_3;//d
|
||||
unsigned char bus_ck804b_4;//e
|
||||
unsigned char bus_ck804b_5;//f
|
||||
unsigned apicid_ck804;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
unsigned apicid_ck804b;
|
||||
|
||||
unsigned sblk;
|
||||
unsigned pci1234[] =
|
||||
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
0x0000ff0,
|
||||
0x0000ff0,
|
||||
0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0
|
||||
};
|
||||
unsigned hc_possible_num;
|
||||
unsigned sbdn;
|
||||
unsigned hcdn[] =
|
||||
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
|
||||
0x20202020,
|
||||
0x20202020,
|
||||
0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
};
|
||||
unsigned sbdn3;
|
||||
unsigned sbdnb;
|
||||
|
||||
extern void get_sblk_pci1234(void);
|
||||
|
||||
static unsigned get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
|
||||
unsigned apicid_base;
|
||||
|
||||
device_t dev;
|
||||
|
||||
if(get_bus_conf_done==1) return; //do it only once
|
||||
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sbdn = (hcdn[0] & 0xff); // first byte of first chain
|
||||
|
||||
sbdn3 = (hcdn[1] & 0xff);
|
||||
|
||||
sbdnb = (hcdn[2] & 0xff); // first byte of second chain
|
||||
|
||||
// bus_ck804_0 = node_link_to_bus(0, sblk);
|
||||
bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
|
||||
|
||||
/* CK804 */
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_5 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
|
||||
}
|
||||
|
||||
bus_8131_0 = (pci1234[1] >> 16) & 0xff;
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_1 = bus_8131_0+1;
|
||||
bus_8131_2 = bus_8131_0+2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_2 = bus_8131_1+1;
|
||||
}
|
||||
|
||||
/* CK804b */
|
||||
|
||||
if(pci1234[2] & 0f) { //if the second cpu is installed
|
||||
bus_ck804b_0 = (pci1234[2]>>16) & 0xff;
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x09);
|
||||
|
||||
bus_ck804b_1 = bus_ck804b_0+1;
|
||||
bus_ck804b_2 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0b);
|
||||
|
||||
bus_ck804b_2 = bus_ck804b_0+1;
|
||||
bus_ck804b_3 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0c);
|
||||
|
||||
bus_ck804b_4 = bus_ck804b_3+1;
|
||||
}
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0d);
|
||||
|
||||
bus_ck804b_5 = bus_ck804b_4+1;
|
||||
}
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
|
||||
#if 1
|
||||
bus_ck804b_5 = bus_ck804b_4+1;
|
||||
#endif
|
||||
|
||||
bus_isa = bus_ck804b_5+1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(4);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_ck804 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
apicid_ck804b = apicid_base+3;
|
||||
|
||||
}
|
||||
|
|
@ -10,71 +10,6 @@
|
|||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*11, /* there can be total 11 devices on the bus */
|
||||
1, /* Where the interrupt router lies (bus) */
|
||||
((CK804_DEVN_BASE+9)<<3)|0, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x10de, /* Vendor */
|
||||
0x005c, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
#if CK804_DEVN_BASE==0
|
||||
0x31, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
#else
|
||||
0x19,
|
||||
#endif
|
||||
{
|
||||
{1,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x4,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x7,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x0, 0},
|
||||
{0x8,((CK804_DEVN_BASE+9)<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
}
|
||||
};
|
||||
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned reg;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
uint32_t config_map;
|
||||
unsigned dst_node;
|
||||
unsigned dst_link;
|
||||
unsigned bus_base;
|
||||
config_map = pci_read_config32(dev, reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
dst_node = (config_map >> 4) & 7;
|
||||
dst_link = (config_map >> 8) & 3;
|
||||
bus_base = (config_map >> 16) & 0xff;
|
||||
#if 0
|
||||
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||
dst_node, dst_link, bus_base,
|
||||
reg, config_map);
|
||||
#endif
|
||||
if ((dst_node == node) && (dst_link == link))
|
||||
{
|
||||
return bus_base;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
|
|
@ -93,6 +28,29 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
|
|||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern unsigned char bus_ck804_0; //1
|
||||
extern unsigned char bus_ck804_1; //2
|
||||
extern unsigned char bus_ck804_2; //3
|
||||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0; //7
|
||||
extern unsigned char bus_8131_1; //8
|
||||
extern unsigned char bus_8131_2; //9
|
||||
extern unsigned char bus_ck804b_0;//a
|
||||
extern unsigned char bus_ck804b_1;//b
|
||||
extern unsigned char bus_ck804b_2;//c
|
||||
extern unsigned char bus_ck804b_3;//d
|
||||
extern unsigned char bus_ck804b_4;//e
|
||||
extern unsigned char bus_ck804b_5;//f
|
||||
|
||||
extern unsigned pci1234[];
|
||||
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
extern unsigned sbdnb;
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
|
|
@ -104,199 +62,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
uint8_t sum=0;
|
||||
int i;
|
||||
|
||||
unsigned char bus_ck804_0; //1
|
||||
unsigned char bus_ck804_1; //2
|
||||
unsigned char bus_ck804_2; //3
|
||||
unsigned char bus_ck804_3; //4
|
||||
unsigned char bus_ck804_4; //5
|
||||
unsigned char bus_ck804_5; //6
|
||||
unsigned char bus_8131_0; //7
|
||||
unsigned char bus_8131_1; //8
|
||||
unsigned char bus_8131_2; //9
|
||||
unsigned char bus_ck804b_0;//a
|
||||
unsigned char bus_ck804b_1;//b
|
||||
unsigned char bus_ck804b_2;//c
|
||||
unsigned char bus_ck804b_3;//d
|
||||
unsigned char bus_ck804b_4;//e
|
||||
unsigned char bus_ck804b_5;//f
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
|
||||
bus_ck804_0 = node_link_to_bus(0, 0);
|
||||
if (bus_ck804_0 == 0) {
|
||||
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||
bus_ck804_0 = 1;
|
||||
}
|
||||
/* CK804 */
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_5 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_0++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0e);
|
||||
|
||||
bus_8131_0 = bus_ck804_5+1;
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_1 = bus_8131_0+1;
|
||||
bus_8131_2 = bus_8131_0+2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_0++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_2 = bus_8131_1+1;
|
||||
bus_ck804b_0 = bus_8131_1+2;
|
||||
}
|
||||
|
||||
/* CK804b */
|
||||
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x09);
|
||||
|
||||
bus_ck804b_1 = bus_ck804b_0+1;
|
||||
bus_ck804b_2 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0b);
|
||||
|
||||
bus_ck804b_2 = bus_ck804b_0+1;
|
||||
bus_ck804b_3 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0c);
|
||||
|
||||
bus_ck804b_4 = bus_ck804b_3+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0d);
|
||||
|
||||
bus_ck804b_5 = bus_ck804b_4+1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0e);
|
||||
#if 1
|
||||
bus_ck804b_5 = bus_ck804b_0+1;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
|
|
@ -312,7 +78,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_ck804_0;
|
||||
pirq->rtr_devfn = ((CK804_DEVN_BASE+9)<<3)|0;
|
||||
pirq->rtr_devfn = ((sbdn+9)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
|
|
@ -326,35 +92,37 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
pirq_info = (void *) ( &pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
//pci bridge
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//pcix bridge
|
||||
write_pirq_info(pirq_info, bus_8131_0, (1<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
if(pci1234[2] & 0xf) {
|
||||
//second pci beidge
|
||||
write_pirq_info(pirq_info, bus_ck804b_0, ((CK804_DEVN_BASE+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
}
|
||||
#if 0
|
||||
//smbus
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//usb
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//audio
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((CK804_DEVN_BASE+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot1 PCIE x16
|
||||
|
|
@ -369,7 +137,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804b_0, ((CK804_DEVN_BASE+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//Slot3 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||
|
|
|
|||
|
|
@ -4,44 +4,33 @@
|
|||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
extern unsigned char bus_isa;
|
||||
extern unsigned char bus_ck804_0; //1
|
||||
extern unsigned char bus_ck804_1; //2
|
||||
extern unsigned char bus_ck804_2; //3
|
||||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0; //7
|
||||
extern unsigned char bus_8131_1; //8
|
||||
extern unsigned char bus_8131_2; //9
|
||||
extern unsigned char bus_ck804b_0;//a
|
||||
extern unsigned char bus_ck804b_1;//b
|
||||
extern unsigned char bus_ck804b_2;//c
|
||||
extern unsigned char bus_ck804b_3;//d
|
||||
extern unsigned char bus_ck804b_4;//e
|
||||
extern unsigned char bus_ck804b_5;//f
|
||||
extern unsigned apicid_ck804;
|
||||
extern unsigned apicid_8131_1;
|
||||
extern unsigned apicid_8131_2;
|
||||
extern unsigned apicid_ck804b;
|
||||
|
||||
extern unsigned pci1234[];
|
||||
|
||||
static unsigned node_link_to_bus(unsigned node, unsigned link)
|
||||
{
|
||||
device_t dev;
|
||||
unsigned reg;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
|
||||
uint32_t config_map;
|
||||
unsigned dst_node;
|
||||
unsigned dst_link;
|
||||
unsigned bus_base;
|
||||
config_map = pci_read_config32(dev, reg);
|
||||
if ((config_map & 3) != 3) {
|
||||
continue;
|
||||
}
|
||||
dst_node = (config_map >> 4) & 7;
|
||||
dst_link = (config_map >> 8) & 3;
|
||||
bus_base = (config_map >> 16) & 0xff;
|
||||
#if 0
|
||||
printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
|
||||
dst_node, dst_link, bus_base,
|
||||
reg, config_map);
|
||||
#endif
|
||||
if ((dst_node == node) && (dst_link == link))
|
||||
{
|
||||
return bus_base;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
extern unsigned sbdn;
|
||||
extern unsigned hcdn[];
|
||||
extern unsigned sbdn3;
|
||||
extern unsigned sbdnb;
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
|
|
@ -51,28 +40,7 @@ void *smp_write_config_table(void *v)
|
|||
struct mp_config_table *mc;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_ck804_0; //1
|
||||
unsigned char bus_ck804_1; //2
|
||||
unsigned char bus_ck804_2; //3
|
||||
unsigned char bus_ck804_3; //4
|
||||
unsigned char bus_ck804_4; //5
|
||||
unsigned char bus_ck804_5; //6
|
||||
unsigned char bus_8131_0; //7
|
||||
unsigned char bus_8131_1; //8
|
||||
unsigned char bus_8131_2; //9
|
||||
unsigned char bus_ck804b_0;//a
|
||||
unsigned char bus_ck804b_1;//b
|
||||
unsigned char bus_ck804b_2;//c
|
||||
unsigned char bus_ck804b_3;//d
|
||||
unsigned char bus_ck804b_4;//e
|
||||
unsigned char bus_ck804b_5;//f
|
||||
unsigned apicid_base;
|
||||
unsigned apicid_ck804;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
unsigned apicid_ck804b;
|
||||
|
||||
int i;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
|
@ -93,188 +61,7 @@ void *smp_write_config_table(void *v)
|
|||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
|
||||
bus_ck804_0 = node_link_to_bus(0, 0);
|
||||
if (bus_ck804_0 == 0) {
|
||||
printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
|
||||
bus_ck804_0 = 1;
|
||||
}
|
||||
/* CK804 */
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_5 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_0++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0e);
|
||||
|
||||
bus_8131_0 = bus_ck804_5+1;
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_8131_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_1 = bus_8131_0+1;
|
||||
bus_8131_2 = bus_8131_0+2;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_0++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
|
||||
|
||||
bus_8131_2 = bus_8131_1+1;
|
||||
bus_ck804b_0 = bus_8131_1+2;
|
||||
}
|
||||
|
||||
/* CK804b */
|
||||
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x09);
|
||||
|
||||
bus_ck804b_1 = bus_ck804b_0+1;
|
||||
bus_ck804b_2 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0b);
|
||||
|
||||
bus_ck804b_2 = bus_ck804b_0+1;
|
||||
bus_ck804b_3 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0c);
|
||||
|
||||
bus_ck804b_4 = bus_ck804b_3+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0d);
|
||||
|
||||
bus_ck804b_5 = bus_ck804b_4+1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
|
||||
if (dev) {
|
||||
bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0e);
|
||||
#if 1
|
||||
bus_ck804b_5 = bus_ck804b_0+1;
|
||||
#endif
|
||||
|
||||
bus_isa = bus_ck804b_5+1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
|
|
@ -284,28 +71,19 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(4);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_ck804 = apicid_base;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
apicid_ck804b = apicid_base+3;
|
||||
// smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
uint32_t dword;
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE+ 0x1,0));
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
|
||||
}
|
||||
|
||||
|
||||
dword = 0x0000d218;
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
|
||||
|
|
@ -317,14 +95,14 @@ void *smp_write_config_table(void *v)
|
|||
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x1,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x2,1));
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
|
|
@ -332,7 +110,8 @@ void *smp_write_config_table(void *v)
|
|||
}
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x1,0));
|
||||
if(pci1234[2] & 0xf) {
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
|
|
@ -349,6 +128,7 @@ void *smp_write_config_table(void *v)
|
|||
pci_write_config32(dev, 0x84, dword);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -366,81 +146,74 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_ck804, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa);
|
||||
// Onboard ck804 smbus
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
|
||||
// 10
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
// Onboard ck804 USB 1.1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
// Onboard ck804 USB 2
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+4)<<2)|0, apicid_ck804, 0x14); // 20
|
||||
// Onboard ck804 Audio
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
// Onboard ck804 SATA 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
// Onboard ck804 SATA 1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
// Onboard ck804 NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
|
||||
#if CK804_DEVN_BASE == 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // 19
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // 16
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // 17
|
||||
#else
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); // 18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); // 19
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); // 16
|
||||
#endif
|
||||
//Slot 1 PCIE x16
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
//Onboard Firewire
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // 16
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // 17
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // 18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // 19
|
||||
//Slot 2 PCI 32
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
|
||||
}
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((CK804_DEVN_BASE+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
|
||||
|
||||
#if CK804_DEVN_BASE == 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x12);//18+24+4+4=50
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x13); // 19
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x10); // 16
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x11); // 17
|
||||
#else
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x10);
|
||||
#endif
|
||||
if(pci1234[2] & 0xf) {
|
||||
//Onboard ck804b NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
|
||||
|
||||
//Slot 3 PCIE x16
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
|
||||
}
|
||||
}
|
||||
|
||||
//Channel B of 8131
|
||||
|
||||
//Slot 4 PCI-X 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|0, apicid_8131_2, 0x0); //24+4 = 28
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|1, apicid_8131_2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|2, apicid_8131_2, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|3, apicid_8131_2, 0x3); //
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
|
||||
}
|
||||
|
||||
//Slot 5 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x1); //24+4+1 = 29
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|2, apicid_8131_2, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|3, apicid_8131_2, 0x0);//
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
|
||||
}
|
||||
|
||||
//OnBoard LSI SCSI
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x2); // 24+4+2 = 30
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x3); // 31
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
|
||||
}
|
||||
|
||||
//Channel A of 8131
|
||||
|
||||
//Slot 6 PCIX 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); // 24
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|2, apicid_8131_1, 0x2);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|3, apicid_8131_1, 0x3);//
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
|
||||
}
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
|||
|
|
@ -35,14 +35,6 @@ static void enumerate_ht_chain(void)
|
|||
break;
|
||||
}
|
||||
|
||||
#if CK804_DEVN_BASE==0
|
||||
//CK804 workaround:
|
||||
// CK804 UnitID changes not use
|
||||
if(id == 0x005e10de) {
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
|
||||
pos = 0;
|
||||
hdr_type &= 0x7f;
|
||||
|
|
|
|||
|
|
@ -111,15 +111,6 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid
|
|||
(id == 0x0000ffff) || (id == 0xffff0000)) {
|
||||
continue;
|
||||
}
|
||||
#if 0
|
||||
#if CK804_DEVN_BASE==0
|
||||
//CK804 workaround:
|
||||
// CK804 UnitID changes not use
|
||||
if(id == 0x005e10de) {
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
pos = ht_lookup_slave_capability(dev);
|
||||
if (!pos) {
|
||||
|
|
@ -478,13 +469,6 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
|
|||
break;
|
||||
}
|
||||
|
||||
#if CK804_DEVN_BASE==0
|
||||
//CK804 workaround:
|
||||
// CK804 UnitID changes not use
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if(id != 0x005e10de) {
|
||||
#endif
|
||||
|
||||
/* Update the Unitid of the current device */
|
||||
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
|
||||
flags &= ~0x1f; /* mask out the bse Unit ID */
|
||||
|
|
@ -493,12 +477,6 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
|
|||
|
||||
/* Note the change in device number */
|
||||
dev = PCI_DEV(bus, next_unitid, 0);
|
||||
#if CK804_DEVN_BASE==0
|
||||
}
|
||||
else {
|
||||
dev = PCI_DEV(bus, 0, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Compute the number of unitids consumed */
|
||||
count = (flags >> 5) & 0x1f;
|
||||
|
|
@ -535,12 +513,6 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
|
|||
reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, offs);
|
||||
#endif
|
||||
|
||||
#if CK804_DEVN_BASE==0
|
||||
if(id == 0x005e10de) {
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Remeber the location of the last device */
|
||||
udev = dev;
|
||||
upos = pos;
|
||||
|
|
|
|||
|
|
@ -119,18 +119,31 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
|
|||
|
||||
#define CK804_CHIP_REV 3
|
||||
|
||||
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
|
||||
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
|
||||
#else
|
||||
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
|
||||
#endif
|
||||
|
||||
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
|
||||
#define CK804B_DEVN_BASE 1
|
||||
#else
|
||||
#define CK804B_DEVN_BASE CK804_DEVN_BASE
|
||||
#endif
|
||||
|
||||
|
||||
static void ck804_early_set_port(void)
|
||||
{
|
||||
|
||||
static const unsigned int ctrl_devport_conf[] = {
|
||||
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
|
||||
#if CK804_NUM > 1
|
||||
PCI_ADDR(CK804B_BUSN, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE,
|
||||
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE,
|
||||
#endif
|
||||
|
||||
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
|
||||
#if CK804_NUM > 1
|
||||
PCI_ADDR(CK804B_BUSN, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE,
|
||||
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -144,12 +157,12 @@ static void ck804_early_clear_port(void)
|
|||
static const unsigned int ctrl_devport_conf_clear[] = {
|
||||
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
#if CK804_NUM > 1
|
||||
PCI_ADDR(CK804B_BUSN, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
#endif
|
||||
|
||||
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
#if CK804_NUM > 1
|
||||
PCI_ADDR(CK804B_BUSN, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -164,16 +177,16 @@ static void ck804_early_setup(void)
|
|||
|
||||
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
|
||||
|
||||
|
||||
#if CK804_NUM > 1
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -189,14 +202,14 @@ static void ck804_early_setup(void)
|
|||
|
||||
|
||||
#if CK804_NUM > 1
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -204,8 +217,8 @@ static void ck804_early_setup(void)
|
|||
RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
|
||||
|
||||
#if CK804_NUM > 1
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
|
||||
RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
|
||||
RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -214,9 +227,9 @@ static void ck804_early_setup(void)
|
|||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
|
||||
|
||||
#if CK804_NUM > 1
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -226,9 +239,9 @@ static void ck804_early_setup(void)
|
|||
|
||||
|
||||
#if CK804_NUM > 1
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -271,16 +284,16 @@ static void ck804_early_setup(void)
|
|||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
|
||||
#if CK804_NUM > 1
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -307,11 +320,11 @@ static void ck804_early_setup(void)
|
|||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
|
||||
#if CK804_USE_NIC == 1
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23);
|
||||
#endif
|
||||
|
||||
#if CK804_USE_ACI == 1
|
||||
|
|
@ -326,11 +339,11 @@ static void ck804_early_setup(void)
|
|||
|
||||
#if CK804_NUM > 1
|
||||
#if CK804_USE_NIC == 1
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
|
||||
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,428 @@
|
|||
/*
|
||||
* Copyright 2004 Tyan Computer
|
||||
* by yhlu@tyan.com
|
||||
* 2005.12 yhlu make it for car so it could support more ck804s
|
||||
*/
|
||||
static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
|
||||
{
|
||||
uint32_t dword, dword_old;
|
||||
uint8_t link_type;
|
||||
|
||||
/* This works on an Athlon64 because unimplemented links return 0 */
|
||||
dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20));
|
||||
link_type = dword & 0xff;
|
||||
|
||||
dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20) );
|
||||
|
||||
if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
|
||||
dword = val;
|
||||
}
|
||||
|
||||
if (dword != dword_old) {
|
||||
pci_write_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20), dword);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
static int set_ht_link_ck804(uint8_t ht_c_num)
|
||||
{
|
||||
int reset_needed;
|
||||
uint8_t i;
|
||||
|
||||
reset_needed = 0;
|
||||
|
||||
for (i = 0; i < ht_c_num; i++) {
|
||||
uint32_t reg;
|
||||
uint8_t nodeid, linkn;
|
||||
uint8_t busn;
|
||||
unsigned val;
|
||||
|
||||
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
|
||||
if((reg & 3) != 3) continue;
|
||||
|
||||
nodeid = ((reg & 0xf0)>>4);
|
||||
linkn = ((reg & 0xf00)>>8);
|
||||
busn = (reg & 0xff0000)>>16;
|
||||
|
||||
reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID);
|
||||
if ( (reg & 0xffff) == 0x10de ) {
|
||||
val = 0x01610169;
|
||||
reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
|
||||
}
|
||||
}
|
||||
|
||||
return reset_needed;
|
||||
}
|
||||
|
||||
|
||||
static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
|
||||
{
|
||||
int i;
|
||||
|
||||
unsigned val;
|
||||
val = inl(control);
|
||||
val &= 0xfffffffe;
|
||||
outl(val, control);
|
||||
|
||||
outl(0, index);
|
||||
|
||||
for(i = 0; i < max; i++) {
|
||||
unsigned long reg;
|
||||
|
||||
reg = register_values[i];
|
||||
outl(reg, where);
|
||||
}
|
||||
val = inl(control);
|
||||
val |= 1;
|
||||
outl(val, control);
|
||||
|
||||
}
|
||||
|
||||
#define ANACTRL_IO_BASE 0x3000
|
||||
#define ANACTRL_REG_POS 0x68
|
||||
|
||||
|
||||
#define SYSCTRL_IO_BASE 0x2000
|
||||
#define SYSCTRL_REG_POS 0x64
|
||||
|
||||
/*
|
||||
16 1 1 2 :0
|
||||
8 8 2 2 :1
|
||||
8 8 4 :2
|
||||
8 4 4 4 :3
|
||||
16 4 :4
|
||||
*/
|
||||
|
||||
#ifndef CK804_PCI_E_X
|
||||
#define CK804_PCI_E_X 4
|
||||
#endif
|
||||
|
||||
/* we will use the offset in setup_resource_map_x_offset and setup_resource_map_offset */
|
||||
#define CK804B_ANACTRL_IO_BASE 0x3000
|
||||
#define CK804B_SYSCTRL_IO_BASE 0x2000
|
||||
|
||||
#ifdef CK804B_BUSN
|
||||
#undef CK804B_BUSN
|
||||
#endif
|
||||
#define CK804B_BUSN 0x0
|
||||
|
||||
#ifndef CK804B_PCI_E_X
|
||||
#define CK804B_PCI_E_X 4
|
||||
#endif
|
||||
|
||||
#ifndef CK804_USE_NIC
|
||||
#define CK804_USE_NIC 0
|
||||
#endif
|
||||
|
||||
#ifndef CK804_USE_ACI
|
||||
#define CK804_USE_ACI 0
|
||||
#endif
|
||||
|
||||
#define CK804_CHIP_REV 3
|
||||
|
||||
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
|
||||
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
|
||||
#else
|
||||
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
|
||||
#endif
|
||||
|
||||
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
|
||||
#define CK804B_DEVN_BASE 1
|
||||
#else
|
||||
#define CK804B_DEVN_BASE CK804_DEVN_BASE
|
||||
#endif
|
||||
|
||||
static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
|
||||
{
|
||||
|
||||
static const unsigned int ctrl_devport_conf[] = {
|
||||
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
|
||||
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
|
||||
};
|
||||
|
||||
static const unsigned int ctrl_devport_conf_b[] = {
|
||||
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
|
||||
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
|
||||
};
|
||||
|
||||
int j;
|
||||
for(j = 0; j < ck804_num; j++ ) {
|
||||
if(busn[j]==0) { //sb chain
|
||||
setup_resource_map_offset(ctrl_devport_conf,
|
||||
sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
|
||||
PCI_DEV(busn[j], 0, 0) , io_base[j]);
|
||||
continue;
|
||||
}
|
||||
setup_resource_map_offset(ctrl_devport_conf_b,
|
||||
sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]),
|
||||
PCI_DEV(busn[j], 0, 0) , io_base[j]);
|
||||
}
|
||||
}
|
||||
|
||||
static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
|
||||
{
|
||||
|
||||
static const unsigned int ctrl_devport_conf_clear[] = {
|
||||
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
};
|
||||
|
||||
static const unsigned int ctrl_devport_conf_clear_b[] = {
|
||||
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
|
||||
};
|
||||
|
||||
int j;
|
||||
for(j = 0; j < ck804_num; j++ ) {
|
||||
if(busn[j]==0) { //sb chain
|
||||
setup_resource_map_offset(ctrl_devport_conf_clear,
|
||||
sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
|
||||
PCI_DEV(busn[j], 0, 0) , io_base[j]);
|
||||
continue;
|
||||
}
|
||||
setup_resource_map_offset(ctrl_devport_conf_clear_b,
|
||||
sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]),
|
||||
PCI_DEV(busn[j], 0, 0) , io_base[j]);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base)
|
||||
{
|
||||
|
||||
static const unsigned int ctrl_conf_master[] = {
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
|
||||
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
|
||||
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
|
||||
RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
|
||||
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
|
||||
|
||||
|
||||
#ifdef CK804_MB_SETUP
|
||||
CK804_MB_SETUP
|
||||
#endif
|
||||
|
||||
|
||||
#if CK804_NUM > 1
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
|
||||
|
||||
#endif
|
||||
|
||||
#if CK804_NUM == 1
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
|
||||
|
||||
#endif
|
||||
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
|
||||
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),
|
||||
|
||||
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
|
||||
|
||||
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
|
||||
|
||||
//PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
|
||||
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
|
||||
|
||||
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
|
||||
|
||||
|
||||
//SYSCTRL
|
||||
|
||||
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
|
||||
#if CK804_USE_NIC == 1
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
|
||||
#endif
|
||||
|
||||
#if CK804_USE_ACI == 1
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
|
||||
#endif
|
||||
|
||||
#if CK804_NUM > 1
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
|
||||
#endif
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
static const unsigned int ctrl_conf_slave[] = {
|
||||
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
|
||||
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
|
||||
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
|
||||
RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
|
||||
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
|
||||
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
|
||||
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
|
||||
|
||||
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
|
||||
|
||||
//PANTA RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
|
||||
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
|
||||
|
||||
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
|
||||
|
||||
#if CK804_USE_NIC == 1
|
||||
RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
|
||||
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
int j;
|
||||
|
||||
for(j=0; j<ck804_num; j++) {
|
||||
if(busn[j] == 0) {
|
||||
setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]),
|
||||
PCI_DEV(busn[0],0,0), io_base[0]);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]),
|
||||
PCI_DEV(busn[j],0,0), io_base[j]);
|
||||
}
|
||||
|
||||
for(j=0; j< ck804_num; j++) {
|
||||
// PCI-E (XSPLL) SS table 0x40, x044, 0x48
|
||||
// SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8
|
||||
// CPU (PPLL) SS table 0xc0, 0xc4, 0xc8
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
|
||||
io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
|
||||
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
|
||||
io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
|
||||
//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
|
||||
// io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
static int ck804_early_setup_x(void)
|
||||
{
|
||||
unsigned busn[4];
|
||||
unsigned io_base[4];
|
||||
int ck804_num = 0;
|
||||
int i;
|
||||
|
||||
for(i=0;i<4;i++) {
|
||||
uint32_t id;
|
||||
device_t dev;
|
||||
if(i == 0) { // SB chain
|
||||
dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0);
|
||||
}
|
||||
else {
|
||||
dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0);
|
||||
}
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if(id == 0x005e10de) {
|
||||
busn[ck804_num] = i * 0x40;
|
||||
io_base[ck804_num] = i * 0x4000;
|
||||
ck804_num++;
|
||||
}
|
||||
}
|
||||
|
||||
ck804_early_set_port(ck804_num, busn, io_base);
|
||||
ck804_early_setup(ck804_num, busn, io_base);
|
||||
ck804_early_clear_port(ck804_num, busn, io_base);
|
||||
return set_ht_link_ck804(4);
|
||||
}
|
||||
Loading…
Reference in New Issue