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mb/google/eve: Fix interrupt config for audio devices 

Use the new PAD_CFG_GPI_INT macro to specify the headset codec
interrupt as specifically edge triggered (since it is registered
as EDGE_BOTH in the devicetree) in order to prevent the interrupt
from firing unexpectedly when the system is resuming.

Also change the DSP interrupt to edge triggered since the kernel
is registering with IRQF_TRIGGER_RISING in order to prevent an
interrupt storm when it asserts.

BUG=b:35582164
TEST=manual testing on Eve:
1) ensure the headset codec sends interrupt on insert and remove
2) ensure there is only one interrupt counted when DSP asserts irq

Change-Id: I40a8ee667de653e4e70770cd96b6417442c1b0ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Duncan Laurie 2017-06-30 02:01:02 -07:00
parent f476867af2
commit 9692f31a4f
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/eve/devicetree.cb
View File

@ -323,7 +323,7 @@ chip soc/intel/skylake
chip drivers/spi/acpi chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID" register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""realtek,rt5514"" register "compat_string" = ""realtek,rt5514""
register "irq" = "ACPI_IRQ_LEVEL_HIGH(GPP_F10_IRQ)" register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F10_IRQ)"
device spi 0 on end device spi 0 on end
end end
end # GSPI #0 end # GSPI #0

2
src/mainboard/google/eve/gpio.h
View File

@ -128,7 +128,7 @@ static const struct pad_config gpio_table[] = {
/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), /* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), /* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */ /* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */
/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */
/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ /* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */
/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */ /* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */