mb/google/octopus/variants/fleex: Update Charger throttling settings

Update dptf settings for Charger throttling. Also, update Power
Limit1 minimum value setting from 4.5W to 3W.

BUG=b:112448519
BRANCH=octopus
TEST=Built and tested on Fleex system

Change-Id: I8c2a796ff28254ebef28ed5745b344f925d6e649
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2018-12-05 23:54:00 +05:30 committed by Aaron Durbin
parent a914152fa6
commit 969ed357f8
1 changed files with 7 additions and 3 deletions

View File

@ -26,6 +26,8 @@
#define DPTF_TSR2_PASSIVE 53
#define DPTF_TSR2_CRITICAL 127
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */
Name (CHPS, Package () {
Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
@ -42,8 +44,10 @@ Name (DTRT, Package () {
/* CPU Effect on Temp Sensor 1 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 2 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
#ifdef DPTF_ENABLE_CHARGER
/* Charger Effect on Temp Sensor 2 */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
#endif
})
Name (MPPC, Package ()
@ -51,7 +55,7 @@ Name (MPPC, Package ()
0x2, /* Revision */
Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */
4500, /* PowerLimitMinimum */
3000, /* PowerLimitMinimum */
10000, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */