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soc/intel/skylake: Add RMRRs after all DRHDs 

The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says:

 BIOS implementations must report these remapping structure types in
 numerical order. i.e., All remapping structures of type 0 (DRHD)
 enumerated before remapping structures of type 1 (RMRR), and so forth.

So, update the corresponding code to adhere to the specification.

Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-08-03 12:29:41 +02:00
parent 37799b3439
commit 96a80133e1
1 changed files with 18 additions and 11 deletions
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29
src/soc/intel/skylake/acpi.c
View File

@ -425,22 +425,19 @@ static unsigned long acpi_fill_dmar(unsigned long current)
const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
/* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */
if (igfx_dev && igfx_dev->enabled && gfxvten && const bool emit_igd =
gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) { igfx_dev && igfx_dev->enabled &&
unsigned long tmp = current; gfx_vtbar && gfxvten &&
!MCHBAR32(GFXVTBAR + 4);
/* First, add DRHD entries */
if (emit_igd) {
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
/* Add RMRR entry */
tmp = current;
current += acpi_create_dmar_rmrr(current, 0,
sa_get_gsm_base(), sa_get_tolud_base() - 1);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_rmrr_fixup(tmp, current);
} }
const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
@ -461,6 +458,16 @@ static unsigned long acpi_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current); acpi_dmar_drhd_fixup(tmp, current);
} }
/* Then, add RMRR entries after all DRHD entries */
if (emit_igd) {
const unsigned long tmp = current;
current += acpi_create_dmar_rmrr(current, 0,
sa_get_gsm_base(), sa_get_tolud_base() - 1);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_rmrr_fixup(tmp, current);
}
return current; return current;
} }