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soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function 

This patch refactors the `pmc_lockdown_cfg()` to remove the helper
functions and uses the `setbits32` function to enforce bit locking
as applicable.

This patch also locks PMC features like:
1. Debug mode configuration and host read access to PMC XRAM.
2. PMC soft strap message interface.
3. PMC static function.
and then calls into the PMC IPC function that informs about PCI
enumeration.

Port of -
1. commit 2eec87a553 ("soc/intel/alderlake: Refactor
`pmc_lockdown_cfg` function")
2. commit bae4a0b5a1 ("soc/intel/alderlake: Implement PMC
feature lock")
3. commit c2570dc998 ("soc/intel/alderlake: Implement PMC
soft strap interface lock")
4. commit f021952c40 ("soc/intel/alderlake: Implement PMC
static function lock")
5. commit 4578914153 ("soc/intel/alderlake: Call into PMC
IPC to inform PCI enumeration done")

BUG=none
TEST=Boot to OS on google/rex.

Register values in OS -
# busybox devmem 0xfe0018d4 32 #bit31
0x80000000
# busybox devmem 0xfe001024 32 #bit21,18,17,4
0x00362610
# busybox devmem 0xfe001818 32 #bit27,22
0x2B4F0004
# busybox devmem 0xfe00104c 32 #bit0
0x00000001


Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70132
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kapil Porwal 2022-11-29 18:21:53 +05:30 committed by Felix Held
parent a521d66116
commit 96c605f39a
2 changed files with 22 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/meteorlake/include/soc/pmc.h
View File

@ -51,6 +51,7 @@ extern struct device_operations pmc_ops;
#define SLEEP_AFTER_POWER_FAIL (1 << 0) #define SLEEP_AFTER_POWER_FAIL (1 << 0)
#define GEN_PMCON_B 0x1024 #define GEN_PMCON_B 0x1024
#define ST_FDIS_LOCK (1 << 21)
#define SLP_STR_POL_LOCK (1 << 18) #define SLP_STR_POL_LOCK (1 << 18)
#define ACPI_BASE_LOCK (1 << 17) #define ACPI_BASE_LOCK (1 << 17)
#define PM_DATA_BAR_DIS (1 << 16) #define PM_DATA_BAR_DIS (1 << 16)
@ -76,6 +77,10 @@ extern struct device_operations pmc_ops;
#define PRSTS 0x1810 #define PRSTS 0x1810
#define PM_CFG 0x1818
#define PM_CFG_DBG_MODE_LOCK (1 << 27)
#define PM_CFG_XRAM_READ_DISABLE (1 << 22)
#define S3_PWRGATE_POL 0x1828 #define S3_PWRGATE_POL 0x1828
#define S3DC_GATE_SUS (1 << 1) #define S3DC_GATE_SUS (1 << 1)
#define S3AC_GATE_SUS (1 << 0) #define S3AC_GATE_SUS (1 << 0)
@ -96,7 +101,7 @@ extern struct device_operations pmc_ops;
#define DSX_EN_LAN_WAKE_PIN (1 << 0) #define DSX_EN_LAN_WAKE_PIN (1 << 0)
#define DSX_CFG_MASK (0x1f << 0) #define DSX_CFG_MASK (0x1f << 0)
#define PMSYNC_TPR_CFG 0x18C4 #define PMSYNC_TPR_CFG 0x18d4
#define PCH2CPU_TPR_CFG_LOCK (1 << 31) #define PCH2CPU_TPR_CFG_LOCK (1 << 31)
#define PCH2CPU_TT_EN (1 << 26) #define PCH2CPU_TT_EN (1 << 26)

55
src/soc/intel/meteorlake/lockdown.c
View File

@ -3,6 +3,7 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <intelblocks/cfg.h> #include <intelblocks/cfg.h>
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
#include <intelpch/lockdown.h> #include <intelpch/lockdown.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#include <soc/pm.h> #include <soc/pm.h>
@ -12,51 +13,27 @@
#define PCR_PSTH_CTRLREG 0x1d00 #define PCR_PSTH_CTRLREG 0x1d00
#define PSTH_CTRLREG_IOSFPTCGE (1 << 2) #define PSTH_CTRLREG_IOSFPTCGE (1 << 2)
static void pmc_lock_pmsync(void)
{
uint8_t *pmcbase;
uint32_t pmsyncreg;
pmcbase = pmc_mmio_regs();
pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
}
static void pmc_lock_abase(void)
{
uint8_t *pmcbase;
uint32_t reg32;
pmcbase = pmc_mmio_regs();
reg32 = read32(pmcbase + GEN_PMCON_B);
reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
write32(pmcbase + GEN_PMCON_B, reg32);
}
static void pmc_lock_smi(void)
{
uint8_t *pmcbase;
uint8_t reg8;
pmcbase = pmc_mmio_regs();
reg8 = read8(pmcbase + GEN_PMCON_B);
reg8 |= SMI_LOCK;
write8(pmcbase + GEN_PMCON_B, reg8);
}
static void pmc_lockdown_cfg(int chipset_lockdown) static void pmc_lockdown_cfg(int chipset_lockdown)
{ {
uint8_t *pmcbase = pmc_mmio_regs();
/* PMSYNC */ /* PMSYNC */
pmc_lock_pmsync(); setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
/* Lock down ABASE and sleep stretching policy */ /* Lock down ABASE and sleep stretching policy */
pmc_lock_abase(); setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
pmc_lock_smi(); setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
setbits32(pmcbase + GEN_PMCON_B, ST_FDIS_LOCK);
setbits32(pmcbase + SSML, SSML_SSL_EN);
setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
PM_CFG_XRAM_READ_DISABLE);
}
/* Send PMC IPC to inform about PCI enumeration done */
pmc_send_pci_enum_done();
} }
static void soc_die_lockdown_cfg(void) static void soc_die_lockdown_cfg(void)