From 96cb2522fd05369f9ef58c782204b3ef0fd9749e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 14 Jun 2020 01:19:36 +0300 Subject: [PATCH] sb/intel/i82801dx: Drop smm_setup_structures() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The only board that builds this does not have ACPI S3 support. Also the code is wrong. Change-Id: Ifb8e0ae5b6d862fa6a52b8e08197a84e7da4be36 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/42357 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/i82801dx/smi.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index d7a02ef8bd..fe4f864f4c 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -330,14 +330,3 @@ void aseg_smm_lock(void) printk(BIOS_DEBUG, "Locking SMM.\n"); northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* The GDT or coreboot table is going to live here. But a long time - * after we relocated the GNVS, so this is not troublesome. - */ - *(u32 *)0x500 = (u32)gnvs; - *(u32 *)0x504 = (u32)tcg; - *(u32 *)0x508 = (u32)smi1; - outb(0xea, 0xb2); -}