From 96cd78eae73ff202156bf4af8321dc2d974a4ca8 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 4 Oct 2023 20:18:27 +0200 Subject: [PATCH] sb/intel/bd82x6x/pcie: Drop register write MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The write to register 0x42 has no effect as at this point all of the bits are read-only. Drop the line. Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/78238 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/pcie.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 45ce5aadd3..325bfd2cd0 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -229,10 +229,8 @@ static void pci_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); /* Enable expresscard hotplug events. */ - if (pci_is_hotplugable(dev)) { + if (pci_is_hotplugable(dev)) pci_or_config32(dev, 0xd8, 1 << 30); - pci_write_config16(dev, 0x42, 0x142); - } } static void pch_pcie_enable(struct device *dev)