diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index c81d307f52..c971cd1586 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -25,22 +25,6 @@ static struct device_operations cpu_bus_ops = {
 
 static void enable_dev(struct device *dev)
 {
-	printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n", __FILE__, __func__,
-			dev_name(dev), dev->path.type);
-
-	printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n",
-			pci_read_config16(dev, PCI_VENDOR_ID),
-			pci_read_config16(dev, PCI_DEVICE_ID));
-
-	printk(BIOS_SPEW, "class: 0x%02x %s\nsubclass: 0x%02x %s\n"
-			"prog: 0x%02x\nrevision: 0x%02x\n",
-			pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8,
-			get_pci_class_name(dev),
-			pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff,
-			get_pci_subclass_name(dev),
-			pci_read_config8(dev, PCI_CLASS_PROG),
-			pci_read_config8(dev, PCI_REVISION_ID));
-
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_DOMAIN) {
 		dev->ops = &pci_domain_ops;
@@ -314,7 +298,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_U
 /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
 static void soc_init(void *chip_info)
 {
-	printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__);
 	soc_init_pre_device(chip_info);
 }
 
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 861f160eb8..9bef5e2164 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -32,8 +32,6 @@ static const struct reg_script core_msr_script[] = {
 
 static void soc_core_init(struct device *cpu)
 {
-	printk(BIOS_SPEW, "%s/%s (%s)\n",
-			__FILE__, __func__, dev_name(cpu));
 	printk(BIOS_DEBUG, "Init Braswell core.\n");
 
 	/* Enable the local cpu apics */
@@ -208,8 +206,6 @@ void soc_init_cpus(struct device *dev)
 {
 	struct bus *cpu_bus = dev->link_list;
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	if (mp_init_with_smm(cpu_bus, &mp_ops))
 		printk(BIOS_ERR, "MP initialization failure.\n");
 }
diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c
index 96f1f07036..954b5b4b50 100644
--- a/src/soc/intel/braswell/emmc.c
+++ b/src/soc/intel/braswell/emmc.c
@@ -20,7 +20,6 @@ static void emmc_init(struct device *dev)
 {
 	struct soc_intel_braswell_config *config = config_of(dev);
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
 	printk(BIOS_DEBUG, "eMMC init\n");
 	reg_script_run_on_dev(dev, emmc_ops);
 
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index 0365ea2779..1bd0033313 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -33,22 +33,18 @@ static inline void gfx_run_script(struct device *dev, const struct reg_script *o
 
 static void gfx_pre_vbios_init(struct device *dev)
 {
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
 	printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
 	gfx_run_script(dev, gpu_pre_vbios_script);
 }
 
 static void gfx_post_vbios_init(struct device *dev)
 {
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
 	printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
 	gfx_run_script(dev, gfx_post_vbios_script);
 }
 
 static void gfx_init(struct device *dev)
 {
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	intel_gma_init_igd_opregion();
 
 	if (!CONFIG(RUN_FSP_GOP)) {
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 0fb4ca9bad..4ad91ae470 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -132,13 +132,10 @@ static void lpe_stash_firmware_info(struct device *dev)
 	write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size);
 }
 
-
 static void lpe_init(struct device *dev)
 {
 	struct soc_intel_braswell_config *config = config_of(dev);
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	lpe_stash_firmware_info(dev);
 	setup_codec_clock(dev);
 
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index 323d406d95..7ff42c35df 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -125,9 +125,6 @@ static void lpss_init(struct device *dev)
 	struct soc_intel_braswell_config *config = config_of(dev);
 	int iosf_reg, nvs_index;
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-	printk(BIOS_SPEW, "%s - %s\n", get_pci_class_name(dev), get_pci_subclass_name(dev));
-
 	dev_ctl_reg(dev, &iosf_reg, &nvs_index);
 
 	if (iosf_reg < 0) {
diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c
index c0cf5e4b98..6a719e78a9 100644
--- a/src/soc/intel/braswell/pcie.c
+++ b/src/soc/intel/braswell/pcie.c
@@ -28,7 +28,6 @@ static inline int is_first_port(struct device *dev)
 
 static void pcie_init(struct device *dev)
 {
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
 }
 
 static const struct reg_script no_dev_behind_port[] = {
@@ -42,9 +41,6 @@ static void check_port_enabled(struct device *dev)
 {
 	int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n",
-			__FILE__, __func__, dev_name(dev));
-
 	switch (root_port_offset(dev)) {
 	case PCIE_PORT1_FUNC:
 		/* Port 1 cannot be disabled from strapping config. */
@@ -83,8 +79,6 @@ static void check_device_present(struct device *dev)
 
 	static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW;
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n",
-			__FILE__, __func__, dev_name(dev));
 	/* Set slot implemented. */
 	pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI);
 
@@ -121,8 +115,6 @@ static void check_device_present(struct device *dev)
 
 static void pcie_enable(struct device *dev)
 {
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	if (is_first_port(dev)) {
 		struct soc_intel_braswell_config *config = config_of(dev);
 		uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL);
diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c
index b5e9019d91..d80edecd11 100644
--- a/src/soc/intel/braswell/sata.c
+++ b/src/soc/intel/braswell/sata.c
@@ -14,7 +14,6 @@ typedef struct soc_intel_braswell_config config_t;
 
 static void sata_init(struct device *dev)
 {
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
 }
 
 static void sata_enable(struct device *dev)
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index 6f23fda119..f56f153ce4 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -14,9 +14,6 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
 	struct resource *bar;
 	struct global_nvs *gnvs;
 
-	printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n",
-			__FILE__, __func__, dev_name(dev), iosf_reg, nvs_index);
-
 	/* Find ACPI NVS to update BARs */
 	gnvs = acpi_get_gnvs();
 	if (!gnvs)
diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c
index 34dd8353e0..5d88016619 100644
--- a/src/soc/intel/braswell/sd.c
+++ b/src/soc/intel/braswell/sd.c
@@ -20,8 +20,6 @@ static void sd_init(struct device *dev)
 {
 	struct soc_intel_braswell_config *config = config_of(dev);
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) {
 		printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n");
 		pci_write_config32(dev, CAP_OVERRIDE_LOW, config->sdcard_cap_low);
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 094e1c29fd..87ace88b2b 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -49,16 +49,11 @@ static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode)
 static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr,
 				     unsigned long size)
 {
-	printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n",
-			__FILE__, __func__, dev_name(dev), addr, size);
-
 	mmio_resource(dev, i, addr >> 10, size >> 10);
 }
 
 static void sc_add_mmio_resources(struct device *dev)
 {
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
 	add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
 	add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
@@ -207,9 +202,6 @@ static void sc_add_io_resource(struct device *dev, int base, int size, int index
 {
 	struct resource *res;
 
-	printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x, 0x%08x)\n",
-			__FILE__, __func__, dev_name(dev), base, size, index);
-
 	if (io_range_in_default(base, size))
 		return;
 
@@ -223,8 +215,6 @@ static void sc_add_io_resources(struct device *dev)
 {
 	struct resource *res;
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	/* Add the default claimed IO range for the LPC device. */
 	res = new_resource(dev, 0);
 	res->base = LPC_DEFAULT_IO_RANGE_LOWER;
@@ -240,8 +230,6 @@ static void sc_add_io_resources(struct device *dev)
 
 static void sc_read_resources(struct device *dev)
 {
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
@@ -263,8 +251,6 @@ static void sc_init(struct device *dev)
 	const struct soc_irq_route *ir = &global_soc_irq_route;
 	struct soc_intel_braswell_config *config = config_of(dev);
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	/* Set the value for PCI command register. */
 	pci_write_config16(dev, PCI_COMMAND,
 		PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
@@ -325,8 +311,6 @@ static void sc_disable_devfn(struct device *dev)
 	uint32_t mask  = 0;
 	uint32_t mask2 = 0;
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 #define SET_DIS_MASK(name_) \
 	case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
 		mask |= name_ ## _DIS
@@ -410,9 +394,6 @@ static void sc_disable_devfn(struct device *dev)
 static inline void set_d3hot_bits(struct device *dev, int offset)
 {
 	uint32_t reg8;
-
-	printk(BIOS_SPEW, "%s/%s (%s, 0x%08x)\n",
-			__FILE__, __func__, dev_name(dev), offset);
 	printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
 	reg8 = pci_read_config8(dev, offset + 4);
 	reg8 |= 0x3;
@@ -427,8 +408,6 @@ static void hda_work_around(struct device *dev)
 {
 	void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	/* Need to set magic register 0x43 to 0xd7 in config space. */
 	pci_write_config8(dev, 0x43, 0xd7);
 
@@ -448,8 +427,6 @@ static int place_device_in_d3hot(struct device *dev)
 {
 	unsigned int offset;
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	/*
 	 * Parts of the HDA block are used for LPE audio as well.
 	 * Therefore assume the HDA will never be put into D3Hot.
@@ -526,8 +503,6 @@ void southcluster_enable_dev(struct device *dev)
 {
 	uint16_t reg16;
 
-	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
-
 	if (!dev->enabled) {
 		int slot = PCI_SLOT(dev->path.pci.devfn);
 		int func = PCI_FUNC(dev->path.pci.devfn);
@@ -581,8 +556,6 @@ static void finalize_chipset(void *unused)
 
 	struct vscc_config cfg;
 
-	printk(BIOS_SPEW, "%s/%s (%p)\n", __FILE__, __func__, unused);
-
 	/* Set the lock enable on the BIOS control register */
 	write32(bcr, read32(bcr) | BCR_LE);