diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 1685e43e0e..ec60cabbea 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -2,7 +2,6 @@
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <intelblocks/cse.h>
 #include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
@@ -141,8 +140,5 @@ void bootblock_pch_init(void)
 
 	enable_rtc_upper_bank();
 
-	/* initialize Heci interface */
-	heci_init(HECI1_BASE_ADDRESS);
-
 	gspi_early_bar_init();
 }
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 30f65eae01..7e891b19f8 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -4,6 +4,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <fsp/util.h>
+#include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
 #include <memory_info.h>
@@ -127,6 +128,8 @@ void mainboard_romstage_entry(void)
 	systemagent_early_init();
 	/* Program SMBus base address and enable it */
 	smbus_common_init();
+	/* initialize Heci interface */
+	heci_init(HECI1_BASE_ADDRESS);
 	ps = pmc_get_power_state();
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);