soc/amd/common/cpu/tsc: add get_pstate_core_freq for family 15h and 16h
This function will be used in follow-up patches for both the TSC rate calculation and the still to be implemented P state ACPI table generation in coreboot. The was checked against BKDG 52740 Rev 3.05, BKDG #55072 Rev 3.04, and BKDG #50742 Rev 3.08. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9afaa044da994d330c3e546b774eb1f82e4f30e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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@ -39,6 +39,12 @@ config ACPI_CPU_STRING
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endif # SOC_AMD_COMMON_BLOCK_NONCAR
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config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
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bool
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help
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Select this option to include code to calculate the CPU frequency
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from the P state MSR values on AMD CPU families 15h and 16h.
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config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
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bool
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help
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@ -1,17 +1,22 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
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bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
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bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
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verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
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verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
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verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
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romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
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romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
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romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/cpu.h>
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#include <console/console.h>
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#include <soc/msr.h>
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#include <types.h>
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#define PSTATE_DEF_FREQ_DIV_MAX 4
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#define PSTATE_DEF_CORE_FREQ_BASE 100
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#define PSTATE_DEF_CORE_FREQ_ID_OFFSET 0x10
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uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
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{
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uint32_t core_freq, core_freq_mul, core_freq_div;
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/* Core frequency multiplier */
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core_freq_mul = pstate_reg.cpu_fid_0_5;
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/* Core frequency divisor ID */
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core_freq_div = pstate_reg.cpu_dfs_id;
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if (core_freq_div > PSTATE_DEF_FREQ_DIV_MAX) {
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printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to lowest "
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"divider.\n", core_freq_div);
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core_freq_div = 0;
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}
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core_freq = (PSTATE_DEF_CORE_FREQ_BASE *
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(core_freq_mul + PSTATE_DEF_CORE_FREQ_ID_OFFSET)) / (1 << core_freq_div);
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return core_freq;
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}
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@ -26,6 +26,7 @@ config SOC_AMD_STONEYRIDGE
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select SOC_AMD_COMMON_BLOCK_AOAC
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select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
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select SOC_AMD_COMMON_BLOCK_CAR
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select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
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select SOC_AMD_COMMON_BLOCK_HDA
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select SOC_AMD_COMMON_BLOCK_I2C
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select SOC_AMD_COMMON_BLOCK_IOMMU
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