soc/amd/common/cpu/tsc: add get_pstate_core_freq for family 15h and 16h

This function will be used in follow-up patches for both the TSC rate
calculation and the still to be implemented P state ACPI table
generation in coreboot. The was checked against BKDG 52740 Rev 3.05,
BKDG #55072 Rev 3.04, and BKDG #50742 Rev 3.08.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9afaa044da994d330c3e546b774eb1f82e4f30e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-03-24 16:55:50 +01:00
parent a63f859553
commit 96fd62f239
4 changed files with 44 additions and 0 deletions

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@ -39,6 +39,12 @@ config ACPI_CPU_STRING
endif # SOC_AMD_COMMON_BLOCK_NONCAR
config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
bool
help
Select this option to include code to calculate the CPU frequency
from the P state MSR values on AMD CPU families 15h and 16h.
config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
bool
help

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@ -1,17 +1,22 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c

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@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/cpu.h>
#include <console/console.h>
#include <soc/msr.h>
#include <types.h>
#define PSTATE_DEF_FREQ_DIV_MAX 4
#define PSTATE_DEF_CORE_FREQ_BASE 100
#define PSTATE_DEF_CORE_FREQ_ID_OFFSET 0x10
uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_5;
/* Core frequency divisor ID */
core_freq_div = pstate_reg.cpu_dfs_id;
if (core_freq_div > PSTATE_DEF_FREQ_DIV_MAX) {
printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to lowest "
"divider.\n", core_freq_div);
core_freq_div = 0;
}
core_freq = (PSTATE_DEF_CORE_FREQ_BASE *
(core_freq_mul + PSTATE_DEF_CORE_FREQ_ID_OFFSET)) / (1 << core_freq_div);
return core_freq;
}

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@ -26,6 +26,7 @@ config SOC_AMD_STONEYRIDGE
select SOC_AMD_COMMON_BLOCK_AOAC
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_CAR
select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
select SOC_AMD_COMMON_BLOCK_HDA
select SOC_AMD_COMMON_BLOCK_I2C
select SOC_AMD_COMMON_BLOCK_IOMMU