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google/chell: Minor updates from EVT and FSP 1.8.0 

- Add pullup on LPC address lines for leakage
- Configure PCH_WP early so it gets set properly in VBNV
- Disable SD card reader in favor of USB

BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell EVT

Change-Id: Ibac79c6cbef0515b1e8a513cfde5fee184e4c70a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebd0c16a6009b74d3c6c36878c502fda9bb3020d
Original-Change-Id: If2bc4eb546a1aab50d3688b6e92f8c38214c9cca
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317241
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12979
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Duncan Laurie 2015-12-10 00:59:27 -08:00 committed by Patrick Georgi
parent 15144d5500
commit 970132f725
2 changed files with 7 additions and 6 deletions
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4
src/mainboard/google/chell/devicetree.cb
View File

@ -36,7 +36,7 @@ chip soc/intel/skylake
register "Cio2Enable" = "0" register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1" register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "2" register "ScsSdCardEnabled" = "0"
register "IshEnable" = "0" register "IshEnable" = "0"
register "PttSwitch" = "0" register "PttSwitch" = "0"
register "InternalGfx" = "1" register "InternalGfx" = "1"
@ -118,7 +118,7 @@ chip soc/intel/skylake
device pci 1e.3 off end # GSPI #1 device pci 1e.3 off end # GSPI #1
device pci 1e.4 on end # eMMC device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO device pci 1e.5 off end # SDIO
device pci 1e.6 on end # SDCard device pci 1e.6 off end # SDCard
device pci 1f.0 on device pci 1f.0 on
chip drivers/pc80/tpm chip drivers/pc80/tpm
device pnp 0c31.0 on end device pnp 0c31.0 on end

9
src/mainboard/google/chell/gpio.h
View File

@ -60,10 +60,10 @@
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
/* PIRQA# */ /* GPP_A7 */ /* PIRQA# */ /* GPP_A7 */
@ -234,6 +234,7 @@ static const struct pad_config gpio_table[] = {
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
}; };
#endif #endif