sb/intel/i82371eb: Rework ACPI tables
Rework ACPI tables based on a mix of previous work on asus/p2b, other boards in tree with better ACPI support, and OEM BIOS. To be pulled in by DSDTs of mainboards using this southbridge. Disable on-the-fly generation of mainboard _CRS node. It is not working as it should and causes runtime errors when booting Linux. This node to be included in mainboard DSDTs in followup patches. Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Keith Hui
Stefan Reinauer
parent
9d0aa99c5e
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2017 Keith Hui <buurin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Declares assorted devices that falls under this southbridge.
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*/
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#include "southbridge/intel/i82371eb/i82371eb.h"
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OperationRegion (S1XX, PCI_Config, 0xB2, 0x01)
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Field (S1XX, ByteAcc, NoLock, Preserve)
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{
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FXS1, 8
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}
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/* 8259-compatible Programmable Interrupt Controller */
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Device (PIC)
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{
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Name (_HID, EisaId ("PNP0000") )
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x0020, 0x0020, 0x01, 0x02, )
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IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02, )
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IRQNoFlags () {2}
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})
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}
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/* PC-class DMA Controller */
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Device (DMA1)
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{
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Name (_HID, EisaId ("PNP0200") )
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Name (_CRS, ResourceTemplate ()
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{
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DMA (Compatibility, BusMaster, Transfer8, ) {4}
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IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,)
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IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,)
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IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,)
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IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20,)
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})
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}
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/* PC-class System Timer */
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Device (TMR)
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{
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Name (_HID, EisaId ("PNP0100"))
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16,0x0040,0x0040,0x01,0x04,)
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IRQNoFlags () {0}
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})
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}
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/* AT Real-Time Clock */
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Device (RTC)
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{
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Name (_HID, EisaId ("PNP0B00") )
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16,0x0070,0x0070,0x01,0x04,)
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IRQNoFlags () {8}
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})
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}
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Device (SPKR)
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{
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Name (_HID, EisaId ("PNP0800"))
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16,0x0061,0x0061,0x01,0x01,)
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})
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}
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/* x87-compatible Floating Point Processing Unit */
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Device (COPR)
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{
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Name (_HID, EisaId ("PNP0C04") )
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16,0x00F0,0x00F0,0x01,0x10,)
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IRQNoFlags () {13}
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})
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}
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@ -0,0 +1,60 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Name(IRQB, ResourceTemplate(){
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IRQ(Level,ActiveLow,Shared){}
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})
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Name(IRQP, ResourceTemplate(){
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IRQ(Level,ActiveLow,Shared){3, 4, 5, 6, 7, 10, 11, 12, 14, 15}
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})
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/* adapted from ma78gm/dsdt.asl */
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#define PCI_INTX_DEV(intx, pinx, uid) \
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Device(intx) { \
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Name(_HID, EISAID("PNP0C0F")) \
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Name(_UID, uid) \
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\
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Method(_STA, 0) { \
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If (And(pinx, 0x80)) { \
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Return(0x09) \
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} \
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Return(0x0B) \
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} \
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\
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Method(_DIS ,0) { \
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Store(0x80, pinx) \
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} \
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\
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Method(_PRS ,0) { \
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Return(IRQP) \
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} \
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\
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Method(_CRS ,0) { \
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CreateWordField(IRQB, 1, IRQN) \
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ShiftLeft(1, And(pinx, 0x0f), IRQN) \
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Return(IRQB) \
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} \
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\
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Method(_SRS, 1) { \
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CreateWordField(ARG0, 1, IRQM) \
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\
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/* Use lowest available IRQ */ \
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FindSetRightBit(IRQM, Local0) \
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if (Local0) { \
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Decrement(Local0) \
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} \
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Store(Local0, pinx) \
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} \
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} \
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