Add support for the MSI MS-7260 (K9N Neo) mainboard.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
420f6abc11
commit
970d06b10d
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##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
|
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
|
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if USE_FAILOVER_IMAGE
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default ROM_SECTION_SIZE = FAILOVER_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
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else
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
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else
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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end
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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default XIP_ROM_SIZE = 65536
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if USE_FAILOVER_IMAGE
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default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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else
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if USE_FALLBACK_IMAGE
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default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
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else
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default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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end
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end
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arch i386 end
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driver mainboard.o
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object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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# object reset.o
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./cache_as_ram_auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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else
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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end
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if USE_FAILOVER_IMAGE
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else
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if CONFIG_AP_CODE_IN_CAR
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makerule ./apc_auto.o
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depends "$(MAINBOARD)/apc_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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ldscript /arch/i386/init/ldscript_apc.lb
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end
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end
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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mainboardinit southbridge/nvidia/mcp55/id.inc
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ldscript /southbridge/nvidia/mcp55/id.lds
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# ROMSTRAP table for MCP55.
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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end
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if USE_DCACHE_RAM
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mainboardinit cpu/amd/car/cache_as_ram.inc
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end
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover_failover.lds
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end
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end
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else
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if USE_FALLBACK_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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end
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end
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end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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initobject cache_as_ram_auto.o
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else
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mainboardinit ./cache_as_ram_auto.inc
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end
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end
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if CONFIG_CHIP_NAME
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config chip.h
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end
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chip northbridge/amd/amdk8/root_complex # Root complex
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device apic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_AM2 # CPU
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8 # Northbridge / mc0
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device pci 18.0 on
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# Devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/mcp55 # Southbridge
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/winbond/w83627ehg # Super I/O
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device pnp 4e.5 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.6 off # Com2 / IrDA
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 4e.7 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.8 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 4e.b on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 4e.c on # PS/2 mouse
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irq 0x70 = 12
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end
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end
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end
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device pci 1.1 on # SM 0
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chip drivers/generic/generic # DIMM 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic # DIMM 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic # DIMM 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic # DIMM 0-1-1
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device i2c 53 on end
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end
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# TODO: Needed?
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# chip drivers/generic/generic # DIMM 1-0-0
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic # DIMM 1-0-1
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# device i2c 55 on end
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# end
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# chip drivers/generic/generic # DIMM 1-1-0
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# device i2c 56 on end
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# end
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# chip drivers/generic/generic # DIMM 1-1-1
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# device i2c 57 on end
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# end
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end
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# TODO: Check if the stuff below is correct / needed.
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device pci 1.1 on # SM 1
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# PCI device SMBus address will depend on addon PCI device,
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# do we need to scan_smbus_bus?
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# chip drivers/generic/generic # PCIXA Slot1
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic # PCIXB Slot1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic # PCIXB Slot2
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic # PCI Slot1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic # Master MCP55 PCI-E
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic # Slave MCP55 PCI-E
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# device i2c 55 on end
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# end
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chip drivers/generic/generic # MAC EEPROM
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device i2c 51 on end
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end
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end
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 on end # IDE
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device pci 5.0 on end # SATA 0
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device pci 5.1 on end # SATA 1
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device pci 5.2 off end # SATA 2 (N/A on this board)
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device pci 6.0 on end # PCI
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device pci 6.1 on end # AZA (HD Audio)
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device pci 8.0 on end # NIC
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device pci 9.0 off end # NIC (N/A on this board)
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device pci a.0 off end # PCI E 5 (N/A on this board?)
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device pci b.0 on end # PCI E 4
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device pci c.0 on end # PCI E 3
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device pci d.0 on end # PCI E 2
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device pci e.0 on end # PCI E 1
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device pci f.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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# TODO: Check the two lines below.
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register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1
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register "mac_eeprom_addr" = "0x51"
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end
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end
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device pci 18.0 on end # Link 1
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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end
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# TODO
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 on end # pci_regs_all
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# device pnp 0.2 on end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 on end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
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# device pnp 0.7 off end # tsc
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# device pnp 0.8 off end # io
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# device pnp 0.9 off end # io
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# end
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end
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@ -0,0 +1,192 @@
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##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
|
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## (at your option) any later version.
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||||
##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
|
||||
##
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||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses USE_FAILOVER_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_FAILOVER_BOOT
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uses HAVE_HARD_RESET
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_MAX_PHYSICAL_CPUS
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uses CONFIG_LOGICAL_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses FAILOVER_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses LINUXBIOS_EXTRA_VERSION
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uses _RAMBASE
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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uses HAVE_INIT_TIMER # ?
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses CONFIG_CHIP_NAME
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_USBDEBUG_DIRECT
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uses HW_MEM_HOLE_SIZEK
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uses HW_MEM_HOLE_SIZE_AUTO_INC
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uses K8_HT_FREQ_1G_SUPPORT
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uses HT_CHAIN_UNITID_BASE
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uses HT_CHAIN_END_UNITID_BASE
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uses SB_HT_CHAIN_ON_BUS0
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uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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uses DCACHE_RAM_GLOBAL_VAR_SIZE
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uses CONFIG_USE_INIT
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uses SERIAL_CPU_INIT
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uses ENABLE_APIC_EXT_ID
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uses APIC_ID_OFFSET
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uses LIFT_BSP_APIC_ID
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uses CONFIG_PCI_64BIT_PREF_MEM
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uses CONFIG_LB_MEM_TOPK
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uses CONFIG_AP_CODE_IN_CAR
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uses MEM_TRAIN_SEQ
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uses WAIT_BEFORE_CPUS_INIT
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uses CONFIG_USE_PRINTK_IN_CAR
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default ROM_SIZE = 512 * 1024
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default FALLBACK_SIZE = (256 * 1024) - (4 * 1024)
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default FAILOVER_SIZE = 4 * 1024
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default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl.
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default HAVE_FALLBACK_BOOT = 1
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default HAVE_FAILOVER_BOOT = 1
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default HAVE_HARD_RESET = 1
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default HAVE_PIRQ_TABLE = 1
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default IRQ_SLOT_COUNT = 11 # TODO: Check if correct.
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default HAVE_MP_TABLE = 1 # TODO: Check if correct.
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default HAVE_OPTION_TABLE = 1
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default CONFIG_SMP = 1
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default CONFIG_MAX_CPUS = 2
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default CONFIG_MAX_PHYSICAL_CPUS = 1
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default CONFIG_LOGICAL_CPUS = 1
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# default SERIAL_CPU_INIT = 0
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default ENABLE_APIC_EXT_ID = 0
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default APIC_ID_OFFSET = 0x10
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default LIFT_BSP_APIC_ID = 1
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default CONFIG_CHIP_NAME = 1
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# Move the default LinuxBIOS CMOS range off of AMD RTC registers.
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default LB_CKS_RANGE_START = 49
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default LB_CKS_RANGE_END = 122
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default LB_CKS_LOC = 123
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# Memory hole size. 0 means disable, others will enable the hole. In that
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# case, if it is smaller than mmio_basek, it will use mmio_basek instead.
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# default HW_MEM_HOLE_SIZEK = 0x200000 # 2GB
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default HW_MEM_HOLE_SIZEK = 0x100000 # 1GB
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# default HW_MEM_HOLE_SIZEK = 0x80000 # 512MB
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|
||||
# Make auto increase hole size to avoid hole_startk equal to basek so as
|
||||
# to make some kernel happy.
|
||||
# default HW_MEM_HOLE_SIZE_AUTO_INC = 1
|
||||
|
||||
# Opteron K8 1G HT support.
|
||||
default K8_HT_FREQ_1G_SUPPORT = 1
|
||||
|
||||
# HT Unit ID offset, default is 1, the typical one, 0 means only one HT device.
|
||||
default HT_CHAIN_UNITID_BASE = 0
|
||||
|
||||
# Real SB Unit ID, default is 0x20, mean don't touch it at last.
|
||||
# default HT_CHAIN_END_UNITID_BASE = 0x6
|
||||
|
||||
# Make the SB HT chain on bus 0, default is not (0).
|
||||
default SB_HT_CHAIN_ON_BUS0 = 2
|
||||
|
||||
# Only offset for SB chain? Default is yes (1).
|
||||
default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
|
||||
|
||||
# Allow capable device use that above 4GB.
|
||||
# default CONFIG_PCI_64BIT_PREF_MEM = 1
|
||||
|
||||
default CONFIG_CONSOLE_VGA = 1 # Needed for VGA.
|
||||
default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA.
|
||||
default CONFIG_USBDEBUG_DIRECT = 0
|
||||
default USE_DCACHE_RAM = 1
|
||||
default DCACHE_RAM_BASE = 0xc8000
|
||||
default DCACHE_RAM_SIZE = 0x08000
|
||||
default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
|
||||
default CONFIG_USE_INIT = 0
|
||||
default CONFIG_AP_CODE_IN_CAR = 0
|
||||
default MEM_TRAIN_SEQ = 2
|
||||
default WAIT_BEFORE_CPUS_INIT = 0
|
||||
default CONFIG_IOAPIC = 1
|
||||
default MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)"
|
||||
default MAINBOARD_VENDOR = "MSI"
|
||||
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
|
||||
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
default STACK_SIZE = 0x2000
|
||||
default HEAP_SIZE = 0x8000
|
||||
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE)
|
||||
default _RAMBASE = 0x00100000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1 # NRV2B compression
|
||||
# default CONFIG_COMPRESSED_PAYLOAD_LZMA = 1 # LZMA compression
|
||||
default CC = "$(CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_USE_PRINTK_IN_CAR = 1
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default TTYS0_BAUD = 115200
|
||||
default TTYS0_BASE = 0x3f8
|
||||
default TTYS0_LCS = 0x3
|
||||
default DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
|
||||
|
||||
end
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY 1
|
||||
|
||||
#define __ROMCC__
|
||||
|
||||
#define RAMINIT_SYSINFO 1
|
||||
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
|
||||
#define SET_NB_CFG_54 1 /* Used by RAM init. */
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "pc80/serial.c"
|
||||
#if CONFIG_USE_INIT == 0
|
||||
#include "lib/memcpy.c"
|
||||
#endif
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include "northbridge/amd/amdk8/raminit.h"
|
||||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
#include "lib/delay.c"
|
||||
/* #include "cpu/x86/lapic/boot_cpu.c" */
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||
#include "cpu/x86/mtrr.h"
|
||||
#include "cpu/amd/mtrr.h"
|
||||
#include "cpu/x86/tsc.h"
|
||||
#include "northbridge/amd/amdk8/amdk8_f_pci.c"
|
||||
#include "northbridge/amd/amdk8/raminit_f_dqs.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
|
||||
void hardwaremain(int ret_addr)
|
||||
{
|
||||
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
|
||||
DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */
|
||||
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK << 10) -
|
||||
DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */
|
||||
struct node_core_id id;
|
||||
|
||||
id = get_node_core_id_x();
|
||||
|
||||
/* FIXME: For USBDEBUG_DIRECT you need to make sure dbg_info gets
|
||||
* assigned in AP.
|
||||
*/
|
||||
print_debug("CODE IN CACHE ON NODE:");
|
||||
print_debug_hex8(id.nodeid);
|
||||
print_debug("\r\n");
|
||||
|
||||
train_ram(id.nodeid, sysinfo, sysinfox);
|
||||
|
||||
/* Go back, but cannot use stack any more, because we only
|
||||
* keep ret_addr and can not restore esp, and ebp.
|
||||
*/
|
||||
__asm__ __volatile__(
|
||||
"movl %0, %%edi\n\t"
|
||||
"jmp *%%edi\n\t"
|
||||
: : "a" (ret_addr)
|
||||
);
|
||||
}
|
||||
|
||||
struct eregs {
|
||||
uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
|
||||
uint32_t vector;
|
||||
uint32_t error_code;
|
||||
uint32_t eip;
|
||||
uint32_t cs;
|
||||
uint32_t eflags;
|
||||
};
|
||||
|
||||
void x86_exception(struct eregs *info)
|
||||
{
|
||||
while (1)
|
||||
hlt();
|
||||
}
|
||||
|
|
@ -0,0 +1,345 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
|
||||
// #define DEBUG_SMBUS 1
|
||||
// #define RAM_TIMING_DEBUG 1
|
||||
// #define DQS_TRAIN_DEBUG 1
|
||||
// #define RES_DEBUG 1
|
||||
|
||||
#define RAMINIT_SYSINFO 1
|
||||
#define K8_ALLOCATE_IO_RANGE 1
|
||||
// #define K8_SCAN_PCI_BUS 1 /* ? */
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
#define SET_NB_CFG_54 1
|
||||
#endif
|
||||
|
||||
/* Used by init_cpus and fidvid. */
|
||||
#define K8_SET_FIDVID 1
|
||||
|
||||
/* If we want to wait for core1 done before DQS training, set it to 0. */
|
||||
#define K8_SET_FIDVID_CORE0_ONLY 1
|
||||
|
||||
#if K8_REV_F_SUPPORT == 1
|
||||
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
|
||||
#endif
|
||||
|
||||
#define DBGP_DEFAULT 7
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
#if USE_FAILOVER_IMAGE == 0
|
||||
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#if CONFIG_USBDEBUG_DIRECT
|
||||
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
|
||||
#include "pc80/usbdebug_direct_serial.c"
|
||||
#endif
|
||||
#include "ram/ramtest.c"
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
|
||||
#include "northbridge/amd/amdk8/raminit.h"
|
||||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
#include "lib/delay.c"
|
||||
|
||||
#endif
|
||||
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
|
||||
#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
|
||||
|
||||
#if USE_FAILOVER_IMAGE == 0
|
||||
|
||||
#include "cpu/x86/bist.h"
|
||||
#if CONFIG_USE_INIT == 0
|
||||
#include "lib/memcpy.c"
|
||||
#endif
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include "cpu/amd/mtrr/amd_earlymtrr.c"
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
|
||||
/* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
|
||||
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
|
||||
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||
|
||||
static void memreset_setup(void) {}
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl) {}
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
|
||||
|
||||
static inline int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
#include "resourcemap.c"
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
|
||||
#define MCP55_NUM 1
|
||||
#define MCP55_USE_NIC 1
|
||||
#define MCP55_USE_AZA 1
|
||||
#define MCP55_PCI_E_X_0 0
|
||||
|
||||
#define MCP55_MB_SETUP \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
|
||||
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
#include "cpu/amd/model_fxx/fidvid.c"
|
||||
|
||||
#endif
|
||||
|
||||
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
|
||||
|
||||
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
static void sio_setup(void)
|
||||
{
|
||||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
|
||||
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
|
||||
dword |= (1 << 0);
|
||||
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
|
||||
dword |= (1 << 16);
|
||||
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
|
||||
}
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
unsigned int last_boot_normal_x = last_boot_normal();
|
||||
|
||||
/* Is this a CPU only reset? Or is this a secondary CPU? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x)
|
||||
goto normal_image;
|
||||
else
|
||||
goto fallback_image;
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0. */
|
||||
/* Allow the HT devices to be found. */
|
||||
enumerate_ht_chain();
|
||||
|
||||
sio_setup();
|
||||
|
||||
/* Setup the MCP55. */
|
||||
mcp55_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the BIOS? */
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary CPU. How should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
|
||||
normal_image:
|
||||
__asm__ volatile ("jmp __normal_image":
|
||||
:"a" (bist), "b"(cpu_init_detectedx)
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
#if HAVE_FAILOVER_BOOT==1
|
||||
__asm__ volatile ("jmp __fallback_image":
|
||||
:"a" (bist), "b"(cpu_init_detectedx)
|
||||
)
|
||||
#endif
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
#if HAVE_FAILOVER_BOOT == 1
|
||||
#if USE_FAILOVER_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#else
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#else
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if USE_FAILOVER_IMAGE == 0
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr[] = {
|
||||
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
|
||||
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
|
||||
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
struct sys_info *sysinfo =
|
||||
(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
int needs_reset = 0;
|
||||
unsigned bsp_apicid = 0;
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
/* FIXME: This should be part of the Super I/O code/config. */
|
||||
pnp_enter_ext_func_mode(SERIAL_DEV);
|
||||
/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
|
||||
pnp_write_config(SERIAL_DEV, 0x24, 0);
|
||||
w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE);
|
||||
pnp_exit_ext_func_mode(SERIAL_DEV);
|
||||
|
||||
setup_mb_resource_map();
|
||||
uart_init();
|
||||
report_bist_failure(bist); /* Halt upon BIST failure. */
|
||||
#if CONFIG_USBDEBUG_DIRECT
|
||||
mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
|
||||
early_usbdebug_direct_init();
|
||||
#endif
|
||||
console_init();
|
||||
|
||||
print_debug("*sysinfo range: [");
|
||||
print_debug_hex32(sysinfo);
|
||||
print_debug(",");
|
||||
print_debug_hex32((unsigned long)sysinfo + sizeof(struct sys_info));
|
||||
print_debug(")\r\n");
|
||||
|
||||
print_debug("bsp_apicid=");
|
||||
print_debug_hex8(bsp_apicid);
|
||||
print_debug("\r\n");
|
||||
|
||||
#if MEM_TRAIN_SEQ == 1
|
||||
/* In BSP so could hold all AP until sysinfo is in RAM. */
|
||||
set_sysinfo_in_ram(0);
|
||||
#endif
|
||||
|
||||
setup_coherent_ht_domain(); /* Routing table and start other core0. */
|
||||
wait_all_core0_started();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
/* It is said that we should start core1 after all core0 launched
|
||||
* becase optimize_link_coherent_ht is moved out from
|
||||
* setup_coherent_ht_domain, so here need to make sure last core0 is
|
||||
* started, esp for two way system (there may be APIC ID conflicts in
|
||||
* that case).
|
||||
*/
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
/* Set up chains and store link pair for optimization later. */
|
||||
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
|
||||
|
||||
#if K8_SET_FIDVID == 1
|
||||
{
|
||||
msr_t msr = rdmsr(0xc0010042);
|
||||
print_debug("begin msr fid, vid ");
|
||||
print_debug_hex32(msr.hi);
|
||||
print_debug_hex32(msr.lo);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
|
||||
enable_fid_change();
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
{
|
||||
msr_t msr = rdmsr(0xc0010042);
|
||||
print_debug("end msr fid, vid ");
|
||||
print_debug_hex32(msr.hi);
|
||||
print_debug_hex32(msr.lo);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
needs_reset |= optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
needs_reset |= mcp55_early_setup_x();
|
||||
|
||||
/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now. */
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
|
||||
/* Do we need apci timer, tsc...., only debug need it for better output */
|
||||
/* All AP stopped? */
|
||||
// init_timer(); /* Need to use TMICT to synconize FID/VID. */
|
||||
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
|
||||
/* bsp switch stack to RAM and copy sysinfo RAM now. */
|
||||
post_cache_as_ram();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations mainboard_msi_ms7260_ops;
|
||||
|
||||
struct mainboard_msi_ms7260_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
##
|
||||
## This file is part of the LinuxBIOS project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
# TODO: Check and fix up the values as needed.
|
||||
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 dual_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 reserved_memory
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
8 0 200Mhz
|
||||
8 1 166Mhz
|
||||
8 2 133Mhz
|
||||
8 3 100Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/dualcore.h>
|
||||
#endif
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
/* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */
|
||||
// busnum is default.
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_mcp55[8]; // 1
|
||||
unsigned apicid_mcp55;
|
||||
|
||||
unsigned pci1234x[] = {
|
||||
/* Here you only need to set value in pci1234 for HT-IO that could
|
||||
* be installed or not. You may need to preset pci1234 for HTIO board,
|
||||
* please refer to * src/northbridge/amd/amdk8/get_sblk_pci1234.c.
|
||||
*/
|
||||
0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0,
|
||||
// 0x0000ff0
|
||||
};
|
||||
|
||||
unsigned hcdnx[] = {
|
||||
/* HT Chain device num, actually it is unit id base of every ht
|
||||
* device in chain, assume every chain only have 4 ht device at most.
|
||||
*/
|
||||
0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
};
|
||||
|
||||
unsigned bus_type[256];
|
||||
|
||||
extern void get_sblk_pci1234(void);
|
||||
|
||||
static unsigned get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
unsigned int apicid_base, sbdn;
|
||||
device_t dev;
|
||||
int i, j;
|
||||
|
||||
if (get_bus_conf_done == 1)
|
||||
return; /* Do it only once. */
|
||||
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]);
|
||||
for (i = 0; i < sysconf.hc_possible_num; i++) {
|
||||
sysconf.pci1234[i] = pci1234x[i];
|
||||
sysconf.hcdn[i] = hcdnx[i];
|
||||
}
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* First byte of first chain */
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
bus_mcp55[i] = 0;
|
||||
|
||||
for (i = 0; i < 256; i++)
|
||||
bus_type[i] = 0;
|
||||
|
||||
bus_type[0] = 1; /* PCI */
|
||||
|
||||
bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
|
||||
bus_type[bus_mcp55[0]] = 1;
|
||||
|
||||
/* MCP55 */
|
||||
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
|
||||
if (dev) {
|
||||
bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_mcp55[2]++;
|
||||
for (j = bus_mcp55[1]; j < bus_mcp55[2]; j++)
|
||||
bus_type[j] = 1;
|
||||
} else {
|
||||
printk_debug
|
||||
("ERROR - could not find PCI 1:%02x.0, using defaults\n",
|
||||
sbdn + 0x06);
|
||||
|
||||
bus_mcp55[1] = 2;
|
||||
bus_mcp55[2] = 3;
|
||||
}
|
||||
|
||||
for (i = 2; i < 8; i++) {
|
||||
dev = dev_find_slot(bus_mcp55[0],
|
||||
PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
|
||||
if (dev) {
|
||||
bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
for (j = bus_mcp55[i]; j < bus_isa; j++)
|
||||
bus_type[j] = 1;
|
||||
} else {
|
||||
printk_debug
|
||||
("ERROR - could not find PCI %02x:%02x.0, using defaults\n",
|
||||
bus_mcp55[0], sbdn + 0x0a + i - 2);
|
||||
bus_isa = bus_mcp55[i - 1] + 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(1);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_mcp55 = apicid_base + 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
|
||||
uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2,
|
||||
uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
extern unsigned char bus_mcp55[8]; // 1
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
unsigned int slot_num, sbdn;
|
||||
uint8_t *v;
|
||||
uint8_t sum = 0;
|
||||
int i;
|
||||
|
||||
/* Will find out all bus num and apic that share with mptable.c
|
||||
* and mptable.c and acpi_tables.c.
|
||||
*/
|
||||
get_bus_conf();
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be betweeen 0xf0000 and 0x100000. */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *)(addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
pirq->rtr_bus = bus_mcp55[0];
|
||||
pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
|
||||
pirq->exclusive_irqs = 0;
|
||||
pirq->rtr_vendor = 0x10de;
|
||||
pirq->rtr_device = 0x0370; /* TODO: Hm, getpir suggests 0x0364 !? */
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* PCI bridge (00:06.0) */
|
||||
write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
|
||||
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum)
|
||||
pirq->checksum = sum;
|
||||
|
||||
printk_info("done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if CONFIG_CHIP_NAME == 1
|
||||
struct chip_operations mainboard_msi_ms7260_ops = {
|
||||
CHIP_NAME("MSI K9N Neo (MS-7260) Mainboard")
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
extern unsigned char bus_mcp55[8]; // 1
|
||||
extern unsigned apicid_mcp55;
|
||||
extern unsigned bus_type[256];
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "MSI ";
|
||||
static const char productid[12] = "MS-7260 ";
|
||||
struct mp_config_table *mc;
|
||||
unsigned int sbdn;
|
||||
int i, j;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* Initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* Not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
/* Bus: Bus ID Type */
|
||||
/* Define bus and ISA numbers. */
|
||||
for (j = 0; j < 256; j++) {
|
||||
if (bus_type[j])
|
||||
smp_write_bus(mc, j, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
uint32_t dword;
|
||||
|
||||
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res)
|
||||
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
|
||||
|
||||
dword = 0x43c6c643;
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
|
||||
dword = 0x81001a00;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
|
||||
dword = 0xd0001202;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_mcp55, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_mcp55, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_mcp55, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_mcp55, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_mcp55, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_mcp55, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_mcp55, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_mcp55, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_mcp55, 0xf);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 1) << 2) | 1, apicid_mcp55, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 0, apicid_mcp55, 0x16); // 22
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 1, apicid_mcp55, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 6) << 2) | 1, apicid_mcp55, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 0, apicid_mcp55, 0x14); // 20
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 1, apicid_mcp55, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 2, apicid_mcp55, 0x15); // 21
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 8) << 2) | 0, apicid_mcp55, 0x16); // 22
|
||||
|
||||
for (j = 7; j >= 2; j--) {
|
||||
if (!bus_mcp55[j])
|
||||
continue;
|
||||
for (i = 0; i < 4; i++)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2) | i, apicid_mcp55, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4);
|
||||
}
|
||||
|
||||
for (j = 0; j < 2; j++) {
|
||||
for (i = 0; i < 4; i++)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x06 + j) << 2) | i, apicid_mcp55, 0x10 + (2 + i + j) % 4);
|
||||
}
|
||||
|
||||
/* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums. */
|
||||
mc->mpe_checksum =
|
||||
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,283 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 AMD
|
||||
* Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* TODO: This is copied from the GIGABYTE GA-M57SLI-S4 target. */
|
||||
|
||||
static void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
|
||||
};
|
||||
|
||||
int max = sizeof(register_values) / sizeof(register_values[0]);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
##
|
||||
## This file is part of the LinuxBIOS project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
target ms7260
|
||||
mainboard msi/ms7260
|
||||
|
||||
option ROM_SIZE = 512 * 1024
|
||||
|
||||
romimage "normal"
|
||||
option USE_FAILOVER_IMAGE = 0
|
||||
option USE_FALLBACK_IMAGE = 0
|
||||
option ROM_IMAGE_SIZE = 128 * 1024
|
||||
option XIP_ROM_SIZE = 256 * 1024
|
||||
option LINUXBIOS_EXTRA_VERSION = ".0Normal"
|
||||
payload /tmp/filo.elf
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FAILOVER_IMAGE = 0
|
||||
option USE_FALLBACK_IMAGE = 1
|
||||
option ROM_IMAGE_SIZE = 128 * 1024
|
||||
option XIP_ROM_SIZE = 256 * 1024
|
||||
option LINUXBIOS_EXTRA_VERSION = ".0Fallback"
|
||||
payload /tmp/filo.elf
|
||||
end
|
||||
|
||||
romimage "failover"
|
||||
option USE_FAILOVER_IMAGE = 1
|
||||
option USE_FALLBACK_IMAGE = 0
|
||||
option ROM_IMAGE_SIZE = FAILOVER_SIZE
|
||||
option XIP_ROM_SIZE = FAILOVER_SIZE
|
||||
option LINUXBIOS_EXTRA_VERSION = ".0Failover"
|
||||
end
|
||||
|
||||
# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
|
||||
Loading…
Reference in New Issue