soc/amd/common/data_fabric_helper: factor out data_fabric_set_mmio_np
Factor out data_fabric_set_mmio_np and the helper functions it uses into a separate compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I58625c5a038f668f8e30ae29f03402e1e2c4bee3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Felix Held
parent
f64f3d0048
commit
971c9442f6
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@ -2,6 +2,7 @@
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC) += data_fabric_helper.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += domain.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC) += np_region.c
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT),y)
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += pci_segment_multi.c
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@ -3,9 +3,7 @@
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#include <acpi/acpi_device.h>
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#include <amdblocks/data_fabric.h>
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#include <amdblocks/pci_devs.h>
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#include <arch/hpet.h>
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#include <console/console.h>
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#include <cpu/x86/lapic_def.h>
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#include <device/pci_ops.h>
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#include <soc/data_fabric.h>
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#include <soc/pci_devs.h>
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@ -64,117 +62,6 @@ void data_fabric_print_mmio_conf(void)
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}
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}
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static void data_fabric_disable_mmio_reg(unsigned int reg)
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{
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union df_mmio_control ctrl = { .dst_fabric_id = IOMS0_FABRIC_ID };
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data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw);
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data_fabric_broadcast_write32(DF_MMIO_BASE(reg), 0);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), 0);
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}
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static bool is_mmio_reg_disabled(unsigned int reg)
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{
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union df_mmio_control ctrl;
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ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(reg));
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return !(ctrl.we || ctrl.re);
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}
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static int data_fabric_find_unused_mmio_reg(void)
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{
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for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
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if (is_mmio_reg_disabled(i))
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return i;
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}
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return -1;
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}
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void data_fabric_set_mmio_np(void)
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{
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/*
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* Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
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*
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* AGESA has already programmed the NB MMIO routing, however nothing
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* is yet marked as non-posted.
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*
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* If there exists an overlapping routing base/limit pair, trim its
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* base or limit to avoid the new NP region. If any pair exists
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* completely within HPET-LAPIC range, remove it. If any pair surrounds
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* HPET-LAPIC, it must be split into two regions.
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*
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* TODO(b/156296146): Remove the settings from AGESA and allow coreboot
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* to own everything. If not practical, consider erasing all settings
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* and have coreboot reprogram them. At that time, make the source
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* below more flexible.
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* * Note that the code relies on the granularity of the HPET and
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* LAPIC addresses being sufficiently large that the shifted limits
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* +/-1 are always equivalent to the non-shifted values +/-1.
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*/
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unsigned int i;
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int reg;
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uint32_t base, limit;
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union df_mmio_control ctrl;
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const uint32_t np_bot = HPET_BASE_ADDRESS >> DF_MMIO_SHIFT;
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const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> DF_MMIO_SHIFT;
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data_fabric_print_mmio_conf();
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for (i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
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/* Adjust all registers that overlap */
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ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i));
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if (!(ctrl.we || ctrl.re))
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continue; /* not enabled */
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base = data_fabric_broadcast_read32(DF_MMIO_BASE(i));
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limit = data_fabric_broadcast_read32(DF_MMIO_LIMIT(i));
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if (base > np_top || limit < np_bot)
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continue; /* no overlap at all */
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if (base >= np_bot && limit <= np_top) {
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data_fabric_disable_mmio_reg(i); /* 100% within, so remove */
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continue;
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}
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if (base < np_bot && limit > np_top) {
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/* Split the configured region */
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1);
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reg = data_fabric_find_unused_mmio_reg();
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if (reg < 0) {
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/* Although a pair could be freed later, this condition is
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* very unusual and deserves analysis. Flag an error and
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* leave the topmost part unconfigured. */
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printk(BIOS_ERR, "Not enough NB MMIO routing registers\n");
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continue;
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}
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data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_top + 1);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), limit);
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data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw);
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continue;
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}
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/* If still here, adjust only the base or limit */
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if (base <= np_bot)
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1);
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else
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data_fabric_broadcast_write32(DF_MMIO_BASE(i), np_top + 1);
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}
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reg = data_fabric_find_unused_mmio_reg();
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if (reg < 0) {
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printk(BIOS_ERR, "cannot configure region as NP\n");
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return;
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}
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union df_mmio_control np_ctrl = { .dst_fabric_id = IOMS0_FABRIC_ID,
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.np = 1, .we = 1, .re = 1 };
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data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_bot);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), np_top);
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data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), np_ctrl.raw);
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data_fabric_print_mmio_conf();
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}
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static const char *data_fabric_acpi_name(const struct device *dev)
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{
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const char *df_acpi_names[8] = {
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@ -0,0 +1,119 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/data_fabric.h>
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#include <arch/hpet.h>
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#include <console/console.h>
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#include <cpu/x86/lapic_def.h>
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#include <soc/data_fabric.h>
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#include <types.h>
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static void data_fabric_disable_mmio_reg(unsigned int reg)
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{
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union df_mmio_control ctrl = { .dst_fabric_id = IOMS0_FABRIC_ID };
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data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw);
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data_fabric_broadcast_write32(DF_MMIO_BASE(reg), 0);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), 0);
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}
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static bool is_mmio_reg_disabled(unsigned int reg)
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{
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union df_mmio_control ctrl;
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ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(reg));
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return !(ctrl.we || ctrl.re);
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}
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static int data_fabric_find_unused_mmio_reg(void)
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{
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for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
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if (is_mmio_reg_disabled(i))
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return i;
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}
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return -1;
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}
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void data_fabric_set_mmio_np(void)
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{
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/*
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* Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
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*
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* AGESA has already programmed the NB MMIO routing, however nothing
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* is yet marked as non-posted.
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*
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* If there exists an overlapping routing base/limit pair, trim its
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* base or limit to avoid the new NP region. If any pair exists
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* completely within HPET-LAPIC range, remove it. If any pair surrounds
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* HPET-LAPIC, it must be split into two regions.
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*
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* TODO(b/156296146): Remove the settings from AGESA and allow coreboot
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* to own everything. If not practical, consider erasing all settings
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* and have coreboot reprogram them. At that time, make the source
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* below more flexible.
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* * Note that the code relies on the granularity of the HPET and
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* LAPIC addresses being sufficiently large that the shifted limits
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* +/-1 are always equivalent to the non-shifted values +/-1.
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*/
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unsigned int i;
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int reg;
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uint32_t base, limit;
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union df_mmio_control ctrl;
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const uint32_t np_bot = HPET_BASE_ADDRESS >> DF_MMIO_SHIFT;
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const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> DF_MMIO_SHIFT;
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data_fabric_print_mmio_conf();
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for (i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
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/* Adjust all registers that overlap */
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ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i));
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if (!(ctrl.we || ctrl.re))
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continue; /* not enabled */
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base = data_fabric_broadcast_read32(DF_MMIO_BASE(i));
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limit = data_fabric_broadcast_read32(DF_MMIO_LIMIT(i));
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if (base > np_top || limit < np_bot)
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continue; /* no overlap at all */
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if (base >= np_bot && limit <= np_top) {
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data_fabric_disable_mmio_reg(i); /* 100% within, so remove */
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continue;
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}
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if (base < np_bot && limit > np_top) {
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/* Split the configured region */
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1);
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reg = data_fabric_find_unused_mmio_reg();
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if (reg < 0) {
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/* Although a pair could be freed later, this condition is
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* very unusual and deserves analysis. Flag an error and
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* leave the topmost part unconfigured. */
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printk(BIOS_ERR, "Not enough NB MMIO routing registers\n");
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continue;
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}
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data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_top + 1);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), limit);
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data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw);
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continue;
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}
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/* If still here, adjust only the base or limit */
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if (base <= np_bot)
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1);
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else
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data_fabric_broadcast_write32(DF_MMIO_BASE(i), np_top + 1);
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}
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reg = data_fabric_find_unused_mmio_reg();
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if (reg < 0) {
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printk(BIOS_ERR, "cannot configure region as NP\n");
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return;
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}
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union df_mmio_control np_ctrl = { .dst_fabric_id = IOMS0_FABRIC_ID,
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.np = 1, .we = 1, .re = 1 };
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data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_bot);
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data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), np_top);
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data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), np_ctrl.raw);
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data_fabric_print_mmio_conf();
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}
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