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AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.0 

This is required the BLOB change Icb7a4f07
"AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)"

This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the
boards can boot to Windows 8.1. PCIe slots, USB and NIC work.

Change-Id: Ibe141c16f8f9eac2adc5d5f45a1f354fb2a7f33c
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11148
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
WANG Siyuan 2015-08-10 06:43:31 +08:00 committed by Zheng Bao
parent 762cef9198
commit 9763d8e9d1
5 changed files with 86 additions and 35 deletions
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82
src/vendorcode/amd/pi/00660F01/AGESA.h
View File

@ -1189,16 +1189,21 @@ typedef enum {
DDR2_TECHNOLOGY, ///< DDR2 technology
DDR3_TECHNOLOGY, ///< DDR3 technology
GDDR5_TECHNOLOGY, ///< GDDR5 technology
DDR4_TECHNOLOGY, ///< DDR4 technology
UNSUPPORTED_TECHNOLOGY, ///< Unsupported technology
} TECHNOLOGY_TYPE;
/// Low voltage support
typedef enum {
VOLT_INITIAL, ///< Initial value for VDDIO
VOLT1_5, ///< 1.5 Volt
VOLT1_35, ///< 1.35 Volt
VOLT1_25, ///< 1.25 Volt
VOLT_UNSUPPORTED = 0xFF ///< No common voltage found
VOLT_INITIAL, ///< Initial value for VDDIO
VOLT1_5, ///< 1.5 Volt
VOLT1_35, ///< 1.35 Volt
VOLT1_25, ///< 1.25 Volt
VOLT_DDR4_RANGE_START, ///< Start of DDR4 Voltage Range
VOLT1_2 = VOLT_DDR4_RANGE_START, ///< 1.2 Volt
VOLT_TBD1, ///< TBD1 Voltage
VOLT_TBD2, ///< TBD2 Voltage
VOLT_UNSUPPORTED = 0xFF ///< No common voltage found
} DIMM_VOLTAGE;
/// AMP voltage support
@ -1365,23 +1370,15 @@ typedef enum {
#define COFVID_STAT 0xC0010071ul
#define TSC 0x10
//-----------------------------------------------------------------------------
///
/// SPD Data for each DIMM.
///
typedef struct _SPD_DEF_STRUCT_DX {
IN BOOLEAN SpdValid; ///< Indicates that the SPD is valid
IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid
IN UINT32 Adderess; ///< SMBus Address
IN UINT8 Data[512]; ///< Buffer for 256 Bytes of SPD data from DIMM
} SPD_DEF_STRUCT_DX;
//-----------------------------------------------------------------------------
///
/// SPD Data for each DIMM.
///
typedef struct _SPD_DEF_STRUCT {
IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid
IN UINT8 PageAddress; ///< Indicates the 256 Byte EE Page the data belongs to
///< 0 = Lower Page
///< 1 = Upper Page (DDR4 Only)
IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM
} SPD_DEF_STRUCT;
@ -1566,11 +1563,8 @@ typedef struct _CH_DEF_STRUCT {
OUT UINT8 DimmSRTPresent; ///< For each bit n 0..3, 1 = DIMM n supports Extended Temperature Range where 4..7 are reserved
OUT UINT8 DimmASRPresent; ///< For each bit n 0..3, 1 = DIMM n supports Auto Self Refresh where 4..7 are reserved
OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel.
OUT UINT8 DimmThermSensorPresent; ///< For each bit n 0..3, 1 = DIMM n has an On Dimm Thermal Sensor where 4..7 are reserved
OUT UINT8 MaxVref; ///< Maximum Vref Value for channel
OUT UINT8 Reserved[100]; ///< Reserved
} CH_DEF_STRUCT;
@ -1604,6 +1598,9 @@ typedef struct _CH_TIMING_STRUCT {
OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs
OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs
OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs
OUT UINT16 DIMMTrrdL; ///< Minimax TrrdL*40 (ns) of DIMMs
OUT UINT16 DIMMTwtrL; ///< Minimax TtwrL*40 (ns) of DIMMs
OUT UINT16 DIMMTccdL; ///< Minimax TccdL*40 (ns) of DIMMs
OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz
OUT UINT16 Speed; ///< DRAM bus speed in MHz
///< 400 (MHz)
@ -1622,10 +1619,14 @@ typedef struct _CH_TIMING_STRUCT {
OUT UINT8 Trrd; ///< DCT Trrd (busclocks)
OUT UINT8 Twtr; ///< DCT Twtr (busclocks)
OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks)
OUT UINT8 TrrdL; ///< DCT TrrdL (busclocks)
OUT UINT8 TwtrL; ///< DCT TwtrL (busclocks)
OUT UINT8 TccdL; ///< DCT TccdL (busclocks)
OUT UINT16 Trfc0; ///< DCT Logical DIMM0 Trfc (in ns)
OUT UINT16 Trfc1; ///< DCT Logical DIMM1 Trfc (in ns)
OUT UINT16 Trfc2; ///< DCT Logical DIMM2 Trfc (in ns)
OUT UINT16 Trfc3; ///< DCT Logical DIMM3 Trfc (in ns)
OUT UINT16 Trfc4; ///< DCT Trfc4min All DIMMS (in ns) - DDR4 Only
OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT.
///<
OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
@ -1788,7 +1789,7 @@ typedef struct _MEM_PARAMETER_STRUCT {
///<
OUT UINT32 SysLimit; ///< Limit[47:16] (system address).
///<
OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS.
OUT DIMM_VOLTAGE DDRVoltage; ///< Find support voltage and send back to platform BIOS for DDR3 or DDR4.
///<
OUT VDDP_VDDR_VOLTAGE VddpVddrVoltage; ///< For a given configuration, request is made to change the VDDP/VDDR
///< voltage in platform BIOS via AgesaHookBeforeDramInit callout and
@ -1892,7 +1893,15 @@ typedef struct _MEM_PARAMETER_STRUCT {
///< - TRUE =enable
///<
///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE}
// Extended temperature range
// Temperature Controlled Refresh
IN BOOLEAN DramTempControlledRefreshEn; ///< Enable Temperature Controlled Refresh
///< - FALSE = Disable
///< - TRUE = Enable (Default)
///< @BldCfgItem{BLDCFG_DRAM_TEMP_CONTROLLED_REFRESH_EN}
///< If EnableExtendedTemperatureRange is enabled with this feature
///< then CfgDramDoubleRefreshrate must also be enabled.
// Online Spare
@ -2072,13 +2081,12 @@ typedef struct _MEM_PARAMETER_STRUCT {
///< TRUE = Enable, platfrom BIOS requests support for DDR4
///< FALSE = Disable, platform BIOS requests no DDR4 support
///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR4_CAPABLE}
IN BOOLEAN DimmTypeDddr3Capable; ///< Indicates that the system is DDR3 Capable
IN BOOLEAN DimmTypeDddr3Capable; ///< Indicates that the system is DDR3 Capable
///< TRUE = Enable, platfrom BIOS requests support for DDR3
///< FALSE = Disable, platform BIOS requests no DDR3 support
///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE}
IN UINT16 CustomVddioSupport; ///< CustomVddioSupport
///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE}
} MEM_PARAMETER_STRUCT;
@ -2198,6 +2206,8 @@ typedef union {
///< cannot be applied to current configurations.
#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match
#define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue
#define MEM_ALERT_DRAM_DOUBLE_REFRESH_RATE_ENABLED 0x04010300ul ///< CfgDramDoubleRefreshRate has been enabled due
/// to Extended Temperature Range feature
// AGESA_ERROR Memory Errors
#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS
@ -2249,6 +2259,8 @@ typedef union {
#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found
#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found
#define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found
#define MEM_ERROR_CAD_BUS_TMG_NOT_FOUND 0x040E3500ul ///< No CAD Bus Timing Entries found
#define MEM_ERROR_DATA_BUS_CFG_NOT_FOUND 0x040F3500ul ///< No Data Bus Config Entries found
#define MEM_ERROR_NO_2D_WRDAT_WINDOW 0x040D0400ul ///< No 2D WrDat Window
#define MEM_ERROR_NO_2D_WRDAT_HEIGHT 0x040E0400ul ///< No 2D WrDat Height
#define MEM_ERROR_2D_WRDAT_ERROR 0x040F0400ul ///< 2d WrDat Error
@ -2306,7 +2318,7 @@ typedef union {
// AGESA_CRITICAL Memory Errors
#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3
#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00ul ///< Heap allocation error for DMI table for DDR2
#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR4 0x040A1F00ul ///< Heap allocation error for DMI table for DDR4
#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported
#define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info
@ -2886,6 +2898,7 @@ typedef struct {
IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down.
IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default
IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range
IN BOOLEAN CfgDramTempControlledRefreshEn; ///< Temperature Controlled Refresh Rate - @BldCfgItem{BLDCFG_DRAM_TEMP_CONTROLLED_REFRESH_EN}
IN UINT32 CfgPowerDownMode; ///< Power Down Mode.
IN BOOLEAN CfgOnlineSpare; ///< Online Spare.
IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable.
@ -2938,7 +2951,7 @@ typedef struct {
IN UINT8 CfgAbmSupport; ///< Abm Support
IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate
IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control
IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address
///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID
@ -2985,6 +2998,10 @@ typedef struct {
///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable
///< when it is mixed with other technology types.
IN BOOLEAN CfgDimmTypeDdr4Capable; ///< Select DDR4 as technology type that AGESA will enable
///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR4_CAPABLE}
IN BOOLEAN CfgDimmTypeDdr3Capable; ///< Select DDR3 as technology type that AGESA will enable
///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE}
IN BOOLEAN CfgHybridBoostEnable; ///< HyBrid Boost support
///< @BldCfgItem{BLDCFG_HYBRID_BOOST_ENABLE}
IN UINT64 CfgGnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured)
@ -3141,6 +3158,10 @@ typedef struct {
OUT UINT16 T4ProcFamily2; ///< Family 2
OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
OUT CHAR8 T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer
OUT UINT16 T4CoreCount2; ///< Core count 2
OUT UINT16 T4CoreEnabled2; ///< Core Enable 2
OUT UINT16 T4ThreadCount2; ///< Thread count 2
} TYPE4_DMI_INFO;
/// DMI Type 7 - Cache information
@ -3250,7 +3271,12 @@ typedef enum {
Ddr2MemType, ///< Assign 19 to DDR2
Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
Ddr3MemType = 0x18, ///< Assign 24 to DDR3
Fbd2MemType ///< Assign 25 to FBD2
Fbd2MemType, ///< Assign 25 to FBD2
Ddr4MemType, ///< Assign 26 to DDR4
LpDdrMemType, ///< Assign 27 to LPDDR
LpDdr2MemType, ///< Assign 28 to LPDDR2
LpDdr3MemType, ///< Assign 29 to LPDDR3
LpDdr4MemType, ///< Assign 30 to LPDDR4
} DMI_T17_MEMORY_TYPE;
/// DMI Type 17 offset 13h - Type Detail
@ -3270,7 +3296,7 @@ typedef struct {
OUT UINT16 NonVolatile:1; ///< Non-volatile
OUT UINT16 Registered:1; ///< Registered (Buffered)
OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered)
OUT UINT16 Reserved2:1; ///< Reserved
OUT UINT16 LRDIMM:1; ///< LRDIMM
} DMI_T17_TYPE_DETAIL;
/// DMI Type 17 - Memory Device

23
src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h
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@ -69,7 +69,11 @@
// Family 15h equates
#define AMD_FAMILY_15_CZ 0x0004u
#define AMD_FAMILY_CZ (AMD_FAMILY_15_CZ)
#define AMD_FAMILY_15 AMD_FAMILY_15_CZ
#define AMD_FAMILY_15_ST 0x0008u
#define AMD_FAMILY_ST (AMD_FAMILY_15_ST)
#define AMD_FAMILY_15 (AMD_FAMILY_15_CZ | AMD_FAMILY_ST)
// Family Unknown
#define AMD_FAMILY_UNKNOWN 0x8000u
@ -81,12 +85,23 @@
// Family 15h CZ steppings
#define AMD_F15_CZ_A0 0x0001u
#define AMD_F15_CZ_A1 0x0002u
#define AMD_F15_BR_A1 0x0004u
// Family 15h ST steppings
#define AMD_F15_ST_A0 0x0010u
// Family 15h Unknown stepping
#define AMD_F15_UNKNOWN 0x8000u
#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1)
#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax)
// CZ and BR
#define AMD_F15_BR_Ax (AMD_F15_BR_A1)
#define AMD_F15_BR_ALL (AMD_F15_BR_Ax)
#define AMD_F15_ALL AMD_F15_CZ_ALL
#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1 | AMD_F15_BR_Ax)
#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax | AMD_F15_BR_ALL)
// ST
#define AMD_F15_ST_Ax (AMD_F15_ST_A0)
#define AMD_F15_ST_ALL (AMD_F15_ST_Ax)
#define AMD_F15_ALL (AMD_F15_CZ_ALL | AMD_F15_ST_ALL)
#endif // _CPU_FAM_REGISTERS_H_

4
src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h
View File

@ -429,14 +429,14 @@ typedef struct {
#define CPUID_EXT_FAMILY_MASK 0x0FF00000ul
#define CZ_SOCKET_FP4 0
#define ST_SOCKET_FP4 0
#define ST_SOCKET_FT4 3
#define SOCKET_IGNORE 0xF
#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull
#define APIC_EXT_BRDCST_MASK 0x000E0000ul
#define APIC_ENABLE_BIT 0x00000800ul
#ifndef LOCAL_APIC_ADDR
#define LOCAL_APIC_ADDR 0xFEE00000ul
#endif
#define INT_CMD_REG_LO 0x300
#define INT_CMD_REG_HI 0x310
#define REMOTE_MSG_REG 0x380

1
src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h
View File

@ -986,6 +986,7 @@ typedef struct {
VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table
UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option
BOOLEAN PwrDownDisp2ClkPcieR; /// Power down DISP2_CLK and PCIE_RCLK_Output for power savings
BOOLEAN NoClearThermalTripSts; /// Skip clearing ThermalTrip status
} FCH_ACPI;

11
src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h
View File

@ -68,6 +68,11 @@
#define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR
#define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus Offset
#define PMIO_INDEX_PORT 0xCD6 ///Pmio index port
#define PMIO_DATA_PORT 0xCD7 ///Pmio data port
#define PMIO_REG62 0x62 ///PMIOx62
//======================================================================================
//
// Define Mailbox Status field
@ -162,7 +167,7 @@ GetPspMboxStatus (
BOOLEAN
PspBarInitEarly (void);
PspBarInitEarly (VOID);
VOID
PspLibPciIndirectRead (
@ -184,4 +189,8 @@ UINT8
PspLibAccessWidth (
IN ACCESS_WIDTH AccessWidth
);
BOOLEAN
IsS3Resume (VOID);
#endif // _AMD_LIB_H_