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baytrail: add audio clock workaround for LPE 

Apparently the LPE device needs a 25MHz clock. Provide
the work around to enable this clock.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Confirmed setting being applied.

Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175493
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4928
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Aaron Durbin 2013-11-01 14:36:03 -05:00 committed by Aaron Durbin
parent 65ad521f8a
commit 97651c55a3
2 changed files with 54 additions and 0 deletions
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1
src/soc/intel/baytrail/Makefile.inc
View File

@ -35,6 +35,7 @@ ramstage-y += southcluster.c
ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
ramstage-y += sata.c
ramstage-y += acpi.c
ramstage-y += lpe.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c

53
src/soc/intel/baytrail/lpe.c Normal file
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@ -0,0 +1,53 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <baytrail/iosf.h>
#include <baytrail/ramstage.h>
static void lpe_init(device_t dev)
{
uint32_t reg;
/* Work around for Audio Clock. */
reg = iosf_ccu_read(PLT_CLK_CTRL_3);
reg &= ~0xff;
reg |= PLT_CLK_CTRL_25MHZ_FREQ | PLT_CLK_CTRL_SELECT_FREQ;
iosf_ccu_write(PLT_CLK_CTRL_3, reg);
}
static const struct device_operations device_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = NULL,
.init = lpe_init,
.enable = NULL,
.scan_bus = NULL,
.ops_pci = &soc_pci_ops,
};
static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = LPE_DEVID,
};