mb/google/brya/vell: Move WWAN devices for vell
This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are add to overridetree.cb where WWAN is present for vell. BUG=none BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -155,6 +155,31 @@ chip soc/intel/alderlake
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device generic 0 on end
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device generic 0 on end
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end
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end
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end
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end
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device ref pcie_rp6 on
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# Enable WWAN PCIE 6 using clk 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "reset_off_delay_ms" = "20"
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register "srcclk_pin" = "5"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "skip_on_off_support" = "true"
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device generic 0 alias rp6_rtd3 on end
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end
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chip drivers/wwan/fm
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register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
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register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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register "add_acpi_dma_property" = "true"
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use rp6_rtd3 as rtd3dev
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device generic 0 on end
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end
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end
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device ref pcie_rp8 off end
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device ref pcie_rp8 off end
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device ref pcie_rp9 off end
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device ref pcie_rp9 off end
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device ref tcss_dma0 on
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device ref tcss_dma0 on
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