google/link: Use common i915_reg.h.
Checked by comparing binaries and seeing no differences other than build info. Change-Id: Ie702c540a18b50d6da0379f7c4e65adf3e4f18d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6819 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Vladimir Serbinenko
parent
68a57d6e60
commit
9772f8dcac
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@ -1,239 +0,0 @@
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/*
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* Copyright 2013 Google Inc.
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* Copyright © 2008 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#ifndef _DRM_DP_HELPER_H_
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#define _DRM_DP_HELPER_H_
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/* From the VESA DisplayPort spec */
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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#define AUX_I2C_WRITE 0x0
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#define AUX_I2C_READ 0x1
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#define AUX_I2C_STATUS 0x2
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#define AUX_I2C_MOT 0x4
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#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
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#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
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#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
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#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
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#define AUX_I2C_REPLY_ACK (0x0 << 6)
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#define AUX_I2C_REPLY_NACK (0x1 << 6)
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#define AUX_I2C_REPLY_DEFER (0x2 << 6)
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#define AUX_I2C_REPLY_MASK (0x3 << 6)
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/* AUX CH addresses */
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/* DPCD */
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#define DP_DPCD_REV 0x000
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#define DP_MAX_LINK_RATE 0x001
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#define DP_MAX_LANE_COUNT 0x002
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# define DP_MAX_LANE_COUNT_MASK 0x1f
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# define DP_TPS3_SUPPORTED (1 << 6)
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# define DP_ENHANCED_FRAME_CAP (1 << 7)
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#define DP_MAX_DOWNSPREAD 0x003
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# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
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#define DP_NORP 0x004
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#define DP_DOWNSTREAMPORT_PRESENT 0x005
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# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
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# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
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/* 00b = DisplayPort */
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/* 01b = Analog */
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/* 10b = TMDS or HDMI */
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/* 11b = Other */
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# define DP_FORMAT_CONVERSION (1 << 3)
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#define DP_MAIN_LINK_CHANNEL_CODING 0x006
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#define DP_EDP_CONFIGURATION_CAP 0x00d
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
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#define DP_PSR_SUPPORT 0x070
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# define DP_PSR_IS_SUPPORTED 1
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#define DP_PSR_CAPS 0x071
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# define DP_PSR_NO_TRAIN_ON_EXIT 1
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# define DP_PSR_SETUP_TIME_330 (0 << 1)
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# define DP_PSR_SETUP_TIME_275 (1 << 1)
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# define DP_PSR_SETUP_TIME_220 (2 << 1)
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# define DP_PSR_SETUP_TIME_165 (3 << 1)
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# define DP_PSR_SETUP_TIME_110 (4 << 1)
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# define DP_PSR_SETUP_TIME_55 (5 << 1)
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# define DP_PSR_SETUP_TIME_0 (6 << 1)
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# define DP_PSR_SETUP_TIME_MASK (7 << 1)
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# define DP_PSR_SETUP_TIME_SHIFT 1
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/* link configuration */
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#define DP_LINK_BW_SET 0x100
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# define DP_LINK_BW_1_62 0x06
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# define DP_LINK_BW_2_7 0x0a
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# define DP_LINK_BW_5_4 0x14
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#define DP_LANE_COUNT_SET 0x101
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# define DP_LANE_COUNT_MASK 0x0f
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# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
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#define DP_TRAINING_PATTERN_SET 0x102
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# define DP_TRAINING_PATTERN_DISABLE 0
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# define DP_TRAINING_PATTERN_1 1
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# define DP_TRAINING_PATTERN_2 2
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# define DP_TRAINING_PATTERN_3 3
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# define DP_TRAINING_PATTERN_MASK 0x3
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# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
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# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
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# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
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# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
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# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
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# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
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# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
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# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
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# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
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# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
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# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
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#define DP_TRAINING_LANE0_SET 0x103
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#define DP_TRAINING_LANE1_SET 0x104
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#define DP_TRAINING_LANE2_SET 0x105
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#define DP_TRAINING_LANE3_SET 0x106
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# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
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# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
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# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
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# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
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# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
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# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
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#define DP_DOWNSPREAD_CTRL 0x107
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# define DP_SPREAD_AMP_0_5 (1 << 4)
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#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
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# define DP_SET_ANSI_8B10B (1 << 0)
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#define DP_PSR_EN_CFG 0x170
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# define DP_PSR_ENABLE (1 << 0)
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# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
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# define DP_PSR_CRC_VERIFICATION (1 << 2)
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# define DP_PSR_FRAME_CAPTURE (1 << 3)
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#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
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# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
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# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
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# define DP_CP_IRQ (1 << 2)
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# define DP_SINK_SPECIFIC_IRQ (1 << 6)
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#define DP_EDP_CONFIGURATION_SET 0x10a
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#define DP_LANE0_1_STATUS 0x202
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#define DP_LANE2_3_STATUS 0x203
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# define DP_LANE_CR_DONE (1 << 0)
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# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
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# define DP_LANE_SYMBOL_LOCKED (1 << 2)
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#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
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DP_LANE_CHANNEL_EQ_DONE | \
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DP_LANE_SYMBOL_LOCKED)
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#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DP_INTERLANE_ALIGN_DONE (1 << 0)
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#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
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#define DP_LINK_STATUS_UPDATED (1 << 7)
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#define DP_SINK_STATUS 0x205
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#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
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#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
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#define DP_ADJUST_REQUEST_LANE0_1 0x206
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#define DP_ADJUST_REQUEST_LANE2_3 0x207
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# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
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# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
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# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
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# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
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# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
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# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
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# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
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# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
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#define DP_TEST_REQUEST 0x218
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# define DP_TEST_LINK_TRAINING (1 << 0)
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# define DP_TEST_LINK_PATTERN (1 << 1)
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# define DP_TEST_LINK_EDID_READ (1 << 2)
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# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
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#define DP_TEST_LINK_RATE 0x219
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# define DP_LINK_RATE_162 (0x6)
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# define DP_LINK_RATE_27 (0xa)
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#define DP_TEST_LANE_COUNT 0x220
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#define DP_TEST_PATTERN 0x221
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#define DP_TEST_RESPONSE 0x260
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# define DP_TEST_ACK (1 << 0)
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# define DP_TEST_NAK (1 << 1)
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# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
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#define DP_SET_POWER 0x600
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# define DP_SET_POWER_D0 0x1
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# define DP_SET_POWER_D3 0x2
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#define DP_PSR_ERROR_STATUS 0x2006
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# define DP_PSR_LINK_CRC_ERROR (1 << 0)
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# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
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#define DP_PSR_ESI 0x2007
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# define DP_PSR_CAPS_CHANGE (1 << 0)
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#define DP_PSR_STATUS 0x2008
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# define DP_PSR_SINK_INACTIVE 0
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# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
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# define DP_PSR_SINK_ACTIVE_RFB 2
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# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
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# define DP_PSR_SINK_ACTIVE_RESYNC 4
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# define DP_PSR_SINK_INTERNAL_ERROR 7
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# define DP_PSR_SINK_STATE_MASK 0x07
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#define MODE_I2C_START 1
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#define MODE_I2C_WRITE 2
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#define MODE_I2C_READ 4
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#define MODE_I2C_STOP 8
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#endif /* _DRM_DP_HELPER_H_ */
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File diff suppressed because it is too large
Load Diff
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@ -107,12 +107,12 @@ struct iodef iodefs[] = {
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{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0},
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{W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0},
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{R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200},
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{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
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{W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0},
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{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
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{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
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{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
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{W, 1, "", 0x9404, 0x00002000, 0},
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{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
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{W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0},
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{W, 1, "", IVB_CHICKEN3, 0x00000024, 0},
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{W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0},
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{W, 1, "", 0xb01c, 0x3c4fff8c, 0},
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@ -141,7 +141,7 @@ struct iodef iodefs[] = {
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{R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0},
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{W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0},
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{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0},
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{W, 1, "", _TRANSB_CHICKEN2, TRANS_AUTOTRAIN_GEN_STALL_DIS | 0x80000000, 0},
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{W, 1, "", _TRANSB_CHICKEN2, TRANS_CHICKEN2_TIMING_OVERRIDE | 0x80000000, 0},
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{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0},
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{M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0},
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{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0},
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@ -199,13 +199,13 @@ struct iodef iodefs[] = {
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{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
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{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
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{R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
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{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
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{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
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{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0},
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{W, 1, "", _DSPASTRIDE, 0x00002800, 0},
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{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
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{W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0},
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{W, 1, "", _DSPAADDR, 0x00000000, 0},
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{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
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{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
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{R, 1, "", 0x145d10, 0x2010040c, 0},
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{R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0},
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{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
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@ -274,8 +274,8 @@ struct iodef iodefs[] = {
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{R, 4533, "", _PIPEASTAT, 0x00000000, 0},
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{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
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{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0},
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{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
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{W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0},
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{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
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{W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0},
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{R, 1, "", _DSPAADDR, 0x00000000, 0},
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{W, 1, "", _DSPAADDR, 0x00000000, 0},
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{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
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@ -17,8 +17,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "i915_reg.h"
|
||||
#include "drm_dp_helper.h"
|
||||
#include <drivers/intel/gma/i915_reg.h>
|
||||
#include <drivers/intel/gma/drm_dp_helper.h>
|
||||
|
||||
/* things that are, strangely, not defined anywhere? */
|
||||
#define PCH_PP_UNLOCK 0xabcd0000
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||||
|
|
|
|||
Loading…
Reference in New Issue