mb/emulation/qemu-aarch64: Add MMU support
Enable MMU in bootblock. Makes qemu look more similar to real hardware. There's no real need to activate the MMU. Tested on qemu-system-aarch64: 5 page entries are used out of 32. Change-Id: Ifaed9d3cc11520f180a732d51adce634621b5844 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38534 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -5,6 +5,8 @@
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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bootblock-y += bootblock.c
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romstage-y += cbmem.c
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bootblock-y += media.c
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@ -0,0 +1,33 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/mmu.h>
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#include <bootblock_common.h>
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#include <symbols.h>
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void bootblock_mainboard_init(void)
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{
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mmu_init();
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/* Everything below DRAM is device memory */
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mmu_config_range((void *)0, (uintptr_t)_dram, MA_DEV | MA_RW);
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/* Set a dummy value for DRAM. ramstage should update the mapping. */
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mmu_config_range(_dram, 1 * GiB, MA_MEM | MA_RW);
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mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW);
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mmu_config_range(_bootblock, REGION_SIZE(bootblock), MA_MEM | MA_S | MA_RW);
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mmu_config_range(_romstage, REGION_SIZE(romstage), MA_MEM | MA_S | MA_RW);
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mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW);
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mmu_enable();
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}
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@ -27,8 +27,8 @@ SECTIONS
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STACK(0x60020000, 62K)
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FMAP_CACHE(0x6002F800, 2K)
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ROMSTAGE(0x60030000, 128K)
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RAMSTAGE(0x60070000, 16M)
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TTB(0x60070000, 128K)
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RAMSTAGE(0x600b0000, 16M)
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TTB(0x61100000, 16K)
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POSTRAM_CBFS_CACHE(0x61110000, 1M)
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POSTRAM_CBFS_CACHE(0x61200000, 1M)
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}
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