mb/emulation/qemu-aarch64: Add MMU support

Enable MMU in bootblock. Makes qemu look more similar to real hardware.
There's no real need to activate the MMU.

Tested on qemu-system-aarch64: 5 page entries are used out of 32.

Change-Id: Ifaed9d3cc11520f180a732d51adce634621b5844
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38534
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2020-01-23 13:32:08 +01:00 committed by Philipp Deppenwiese
parent e1498ce6da
commit 977b8e83cb
3 changed files with 38 additions and 3 deletions

View File

@ -5,6 +5,8 @@
#
# SPDX-License-Identifier: GPL-2.0-or-later
bootblock-y += bootblock.c
romstage-y += cbmem.c
bootblock-y += media.c

View File

@ -0,0 +1,33 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/mmu.h>
#include <bootblock_common.h>
#include <symbols.h>
void bootblock_mainboard_init(void)
{
mmu_init();
/* Everything below DRAM is device memory */
mmu_config_range((void *)0, (uintptr_t)_dram, MA_DEV | MA_RW);
/* Set a dummy value for DRAM. ramstage should update the mapping. */
mmu_config_range(_dram, 1 * GiB, MA_MEM | MA_RW);
mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW);
mmu_config_range(_bootblock, REGION_SIZE(bootblock), MA_MEM | MA_S | MA_RW);
mmu_config_range(_romstage, REGION_SIZE(romstage), MA_MEM | MA_S | MA_RW);
mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW);
mmu_enable();
}

View File

@ -27,8 +27,8 @@ SECTIONS
STACK(0x60020000, 62K)
FMAP_CACHE(0x6002F800, 2K)
ROMSTAGE(0x60030000, 128K)
RAMSTAGE(0x60070000, 16M)
TTB(0x60070000, 128K)
RAMSTAGE(0x600b0000, 16M)
TTB(0x61100000, 16K)
POSTRAM_CBFS_CACHE(0x61110000, 1M)
POSTRAM_CBFS_CACHE(0x61200000, 1M)
}