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fix small TOLUD issue in i945 raminit (trivial) 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2009-01-20 22:46:52 +00:00 committed by Stefan Reinauer
parent ebb763fecf
commit 977ed2d995
1 changed files with 3 additions and 3 deletions
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6
src/northbridge/intel/i945/raminit.c
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@ -497,7 +497,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
} }
if (sysinfo->memory_frequency && sysinfo->cas) { if (sysinfo->memory_frequency && sysinfo->cas) {
printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n", printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n",
sysinfo->memory_frequency, sysinfo->cas); sysinfo->memory_frequency, sysinfo->cas);
} else { } else {
die("Could not find common memory frequency and CAS\n"); die("Could not find common memory frequency and CAS\n");
@ -1348,11 +1348,11 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
/* Some extra checks needed. See 4.1.26 in the /* Some extra checks needed. See 4.1.26 in the
* 82945G MCH datasheet (30750203) * 82945G MCH datasheet (30750203)
*/ */
pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud); pci_write_config16(PCI_DEV(0,0,0), TOLUD, tolud);
printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0)); printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0)); printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
printk_debug("TOLUD = 0x%02x\n", tolud); printk_debug("TOLUD = 0x%04x\n", tolud);
pci_write_config16(PCI_DEV(0,0,0), TOM, tolud>>3); pci_write_config16(PCI_DEV(0,0,0), TOM, tolud>>3);