soc/qualcomm/sc7280: init eMMC

Use common sdhci driver in coreboot to initialize eMMC for sc7280.
This should allow us to initialize eMMC earlier in the boot process,
taking it out of the critical path.

BUG=b:254092907
BRANCH=None
TEST=emerge-herobrine coreboot chromeos-bootimage

Change-Id: Ifa88da500e82b44d7523f2e68763e01399c89f4d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71829
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2023-01-11 16:10:07 -08:00
parent 8488b5948d
commit 978b47463e
5 changed files with 42 additions and 0 deletions

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@ -21,6 +21,9 @@ config SOC_QUALCOMM_SC7280
select HAVE_UART_SPECIAL
select PCI
select NO_ECAM_MMCONF_SUPPORT
select COMMONLIB_STORAGE
select COMMONLIB_STORAGE_MMC
select SDHCI_CONTROLLER
if SOC_QUALCOMM_SC7280

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@ -55,6 +55,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/display/mdss.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/disp.c
ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
ramstage-$(CONFIG_PCI) += pcie.c
ramstage-$(CONFIG_SDHCI_CONTROLLER) += sdhci.c ../common/storage/sdhci_msm.c
################################################################################

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@ -91,4 +91,7 @@
/* PHY BCR */
#define GCC_PCIE_1_PHY_BCR 0x18E01C
/* eMMC base address */
#define SDC1_HC_BASE 0x007C4000
#endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */

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@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_QUALCOMM_SC7280_SDHCI_H__
#define _SOC_QUALCOMM_SC7280_SDHCI_H__
int qc_emmc_early_init(void);
#endif // _SOC_QUALCOMM_SC7280_SDHCI_H__

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@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <commonlib/sdhci.h>
#include <commonlib/storage.h>
#include <commonlib/storage/sd_mmc.h>
#include <commonlib/storage/sdhci.h>
#include <commonlib/sd_mmc_ctrlr.h>
#include <soc/addressmap.h>
#include <soc/sdhci.h>
#include <soc/sdhci_msm.h>
int qc_emmc_early_init(void)
{
struct sd_mmc_ctrlr *ctrlr;
struct storage_media media = {0};
ctrlr = new_sdhci_msm_host((void *)(uintptr_t)SDC1_HC_BASE);
if (ctrlr == NULL)
return -1;
media.ctrlr = ctrlr;
SET_BUS_WIDTH(ctrlr, 1);
SET_CLOCK(ctrlr, 384 * 1000);
/* Send CMD1 */
return mmc_send_cmd1(&media);
}