diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 6adb8be9ce..9c238ca578 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -274,7 +274,6 @@ void romstage_common(const struct romstage_params *params)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(wake_from_s3);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
 
 static inline void prepare_for_resume(struct romstage_handoff *handoff)
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 2f4a2c118a..e53fca5c0c 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -96,6 +96,8 @@ void run_ramstage(void)
 	struct prog ramstage =
 		PROG_INIT(ASSET_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage");
 
+	timestamp_add_now(TS_END_ROMSTAGE);
+
 	/* Only x86 systems currently take the same firmware path on resume. */
 	if (IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
 		run_ramstage_from_resume(romstage_handoff_find_or_add(),
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 2987db19dd..dfda22e127 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	rs780_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 372074c5ae..9e2e9044b0 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -225,8 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb800_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 2836d672e3..c01ccf0a37 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 631534ec29..3d7c168479 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -333,8 +333,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //	die("After MCT init before CAR disabled.");
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 12c92441ae..924345d51a 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 526d518f0d..3f252abb5f 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -344,7 +344,4 @@ void main(unsigned long bist)
 
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization(s3resume);
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 }
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index cf36a7265c..b35473cd75 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -368,8 +368,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Restore default SuperIO access */
 	outb(0xaa, port);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 6e3f709f3a..bcff9e407e 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index c3bb1caa1c..e49c9b90a1 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index ca9d1b1ed3..35e9e94d74 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -223,8 +223,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	rs780_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 71b2d5fdb4..bace1d06d8 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -227,8 +227,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	rs780_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 06b8d60cff..8ac24f93b8 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -221,8 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index c213d16c16..cd9b79085b 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -221,8 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 1cc2b1145a..6cb42279d1 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c
index e10b3ac782..0f07354526 100644
--- a/src/mainboard/google/cosmos/romstage.c
+++ b/src/mainboard/google/cosmos/romstage.c
@@ -53,7 +53,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c
index 6f3cb77488..b559c85743 100644
--- a/src/mainboard/google/daisy/romstage.c
+++ b/src/mainboard/google/daisy/romstage.c
@@ -179,7 +179,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index e9b4a09859..aa36bc5e75 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -247,6 +247,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index a947c48666..582d9e0322 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -198,5 +198,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 635877b5e4..d5fdfb1f9a 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -278,7 +278,5 @@ void main(void)
 
 	simple_spi_test();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 31b61e2d72..3d18f182b7 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -252,5 +252,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
index 5ccbe3ec23..a8d8f7deb3 100644
--- a/src/mainboard/google/veyron/romstage.c
+++ b/src/mainboard/google/veyron/romstage.c
@@ -111,7 +111,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c
index f243235d7b..e946cc6414 100644
--- a/src/mainboard/google/veyron_brain/romstage.c
+++ b/src/mainboard/google/veyron_brain/romstage.c
@@ -102,7 +102,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c
index e9857b8e0b..0c1bb31fd9 100644
--- a/src/mainboard/google/veyron_danger/romstage.c
+++ b/src/mainboard/google/veyron_danger/romstage.c
@@ -106,7 +106,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c
index f243235d7b..e946cc6414 100644
--- a/src/mainboard/google/veyron_mickey/romstage.c
+++ b/src/mainboard/google/veyron_mickey/romstage.c
@@ -102,7 +102,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c
index 9cdacc3e1a..e845a4228b 100644
--- a/src/mainboard/google/veyron_rialto/romstage.c
+++ b/src/mainboard/google/veyron_rialto/romstage.c
@@ -112,7 +112,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c
index f243235d7b..e946cc6414 100644
--- a/src/mainboard/google/veyron_romy/romstage.c
+++ b/src/mainboard/google/veyron_romy/romstage.c
@@ -102,7 +102,5 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	run_ramstage();
 }
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index ff2ed109ca..62fd6cbe63 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -218,8 +218,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	bcm5785_early_setup();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();
 }
 
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index f8229220b9..6df828b21d 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 92d05189d8..45da7d1fdf 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -306,8 +306,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	*(u32*)cbmem_hob_ptr = (u32)HobListPtr;
 	post_code(0x4f);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index bcf498b7a4..5bdbdc671b 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -256,5 +256,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 35596424e1..ac66ada06f 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -229,8 +229,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 869e020977..57f8542839 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -243,5 +243,4 @@ void main(unsigned long bist)
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 280722fce9..16fa87108c 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -284,6 +284,4 @@ void main(unsigned long bist)
 
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization(s3resume);
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 1e335d33ec..4be1ead914 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -310,6 +310,4 @@ void main(unsigned long bist)
 #if CONFIG_LPC_TPM
 	init_tpm(s3resume);
 #endif
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index e9cd80d0bd..7765812b6f 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -284,7 +284,4 @@ void main(unsigned long bist)
 
 	/* Initialize the internal PCIe links before we go into stage2 */
 	i945_late_initialization(s3resume);
-
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 }
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index ef35fc983e..b8fca64c97 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -243,8 +243,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index 82bacfe1db..074b31c6db 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -297,6 +297,4 @@ void main(unsigned long bist)
 		quick_ram_check();
 	}
 #endif
-
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 015ae08096..f2d5f4ce7f 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -274,5 +274,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 161c8d1f2d..7fa93b800c 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -284,5 +284,4 @@ void main(unsigned long bist)
 	if (CONFIG_LPC_TPM) {
 		init_tpm(boot_mode == 2);
 	}
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 405ec2e4ae..d94d9176fd 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -240,8 +240,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
 	post_code(0x42);     // Should never see this post code.
 }
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index f74decbaac..c79c2b1ca9 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -304,8 +304,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();  /* BSP switch stack to ram, copy then execute CB. */
 	post_code(0x42);  /* Should never see this post code. */
 }
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 1c9fc8d61f..b3174ae097 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -239,8 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sr5650_before_pci_init();
 	sb7xx_51xx_before_pci_init();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 5f49a353c1..1049014407 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -239,8 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index 8912d13429..b38cd7113b 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -96,7 +96,6 @@ void main(unsigned long bist)
 #if CONFIG_EARLY_CBMEM_INIT
 	cbmem_recovery(0);
 #endif
-	timestamp_add_now(TS_END_ROMSTAGE);
 	/* FIXME: See if this is needed or take this out please */
 	/* Disable Memcard and SDIO */
 	pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4));
diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c
index 45f671c6e5..a18c480d3c 100644
--- a/src/northbridge/intel/sandybridge/romstage_native.c
+++ b/src/northbridge/intel/sandybridge/romstage_native.c
@@ -135,5 +135,4 @@ void main(unsigned long bist)
 #endif
 
 	post_code(0x3f);
-	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 7bd2663b25..c7f66bb4a2 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -250,8 +250,6 @@ void romstage_common(struct romstage_params *params)
 
 void asmlinkage romstage_after_car(void)
 {
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 884c274316..5b6d0b30f8 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -132,8 +132,6 @@ void romstage_common(struct romstage_params *params)
 
 void asmlinkage romstage_after_car(void)
 {
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index ee9c9751a8..0d5e85fa67 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -207,8 +207,6 @@ asmlinkage void romstage_after_car(void *chipset_context)
 	soc_after_temp_ram_exit();
 	soc_display_mtrrs();
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	/* Load the ramstage. */
 	copy_and_run();
 	die("ERROR - Failed to load ramstage!");
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index c40f1635da..b5384facb8 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -267,8 +267,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x4f);
 
 	/* Load the ramstage. */
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 3500dfd6e6..bc58b487c0 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -130,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
 	post_code(0x4e);
 
-	timestamp_add_now(TS_END_ROMSTAGE);
-
 	post_code(0x4f);
 
 	/* Load the ramstage. */