Revert "mb/google/brya: Initiate peripheral buses"
This reverts commit 5bb5c43b93.
Reason for revert: Build bot fails.
Change-Id: I8f022514351b37be135d10ef8486e4aa5fd6361b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48980
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
Tim Wawrzynczak
parent
3054a19279
commit
979a071b0e
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@ -3,113 +3,6 @@ chip soc/intel/alderlake
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device lapic 0 on end
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device lapic 0 on end
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end
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end
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2_C0
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register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB2_C1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # USB2_C2
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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# Enable WLAN PCIE 5 using clk 2
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_ENABLED,
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}"
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# Enable WWAN PCIE 6 using clk 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_ENABLED,
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}"
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# Enable SD Card PCIE 8 using clk 3
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_ENABLED | PCIE_RP_HOTPLUG_ENABLED | PCIE_RP_LTR_ENABLED,
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}"
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# Enable NVMe PCIE 9 using clk 1
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_ENABLED | PCIE_RP_LTR_ENABLED,
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}"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoPci,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 1,
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}"
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register "SerialIoGSpiCsState" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 1,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
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#| GSPI1 | Fingerprint MCU |
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#| I2C0 | Audio |
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#| I2C1 | Touchscreen |
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#| I2C2 | SAR0 |
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#| I2C3 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C4 | CAM |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device domain 0 on
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device ref igpu on end
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device ref igpu on end
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device ref dtt on end
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device ref dtt on end
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@ -137,6 +30,7 @@ chip soc/intel/alderlake
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device ref pcie_rp8 on end #PCIE8 SD card
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device ref pcie_rp8 on end #PCIE8 SD card
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device ref pcie_rp9 on end #PCIE9-12 SSD
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device ref pcie_rp9 on end #PCIE9-12 SSD
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device ref uart0 on end
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device ref uart0 on end
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device ref gspi0 on end
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device ref gspi1 on end
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device ref gspi1 on end
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device ref pch_espi on
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device ref pch_espi on
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chip ec/google/chromeec
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chip ec/google/chromeec
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