sb/amd/amd8132: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I83d7025280b75088c37049f34564610612996e1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36965 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
Kyösti Mälkki
parent
b274ccf596
commit
979d4ce02f
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@ -1,2 +0,0 @@
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config SOUTHBRIDGE_AMD_AMD8132
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bool
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@ -1,5 +0,0 @@
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ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y)
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ramstage-y += bridge.c
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endif
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@ -1,424 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005,2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <device/pcix.h>
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#define NMI_OFF 0
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#define NPUML 0xD9 /* Non prefetchable upper memory limit */
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#define NPUMB 0xD8 /* Non prefetchable upper memory base */
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static void amd8132_walk_children(struct bus *bus,
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void (*visit)(struct device *dev, void *ptr), void *ptr)
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{
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struct device *child;
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for (child = bus->children; child; child = child->sibling) {
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if (child->path.type != DEVICE_PATH_PCI) {
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continue;
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}
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if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
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amd8132_walk_children(child->link_list, visit, ptr);
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}
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visit(child, ptr);
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}
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}
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struct amd8132_bus_info {
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unsigned int sstatus;
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unsigned int rev;
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int master_devices;
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int max_func;
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};
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static void amd8132_count_dev(struct device *dev, void *ptr)
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{
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struct amd8132_bus_info *info = ptr;
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/* Don't count pci bridges */
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if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
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info->master_devices++;
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}
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if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
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info->max_func = PCI_FUNC(dev->path.pci.devfn);
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}
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}
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static void amd8132_pcix_tune_dev(struct device *dev, void *ptr)
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{
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struct amd8132_bus_info *info = ptr;
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unsigned int cap;
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unsigned int status, cmd, orig_cmd;
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unsigned int max_read, max_tran;
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int sibs;
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if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
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return;
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}
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cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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if (!cap) {
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return;
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}
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/* How many siblings does this device have? */
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sibs = info->master_devices - 1;
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printk(BIOS_DEBUG, "%s AMD8132 PCI-X tuning\n", dev_path(dev));
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status = pci_read_config32(dev, cap + PCI_X_STATUS);
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orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
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max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
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max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
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if (info->rev == 0x01) { // only a1 need it
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/* Errata #53 Limit the number of split transactions to avoid starvation */
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if (sibs >= 2) {
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/* At most 2 outstanding split transactions when we have
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* 3 or more bus master devices on the bus.
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*/
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if (max_tran > 1) {
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max_tran = 1;
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}
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}
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else if (sibs == 1) {
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/* At most 4 outstanding split transactions when we have
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* 2 bus master devices on the bus.
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*/
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if (max_tran > 3) {
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max_tran = 3;
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}
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}
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else {
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/* At most 8 outstanding split transactions when we have
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* only one bus master device on the bus.
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*/
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if (max_tran > 4) {
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max_tran = 4;
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}
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}
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}
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if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
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cmd &= ~PCI_X_CMD_MAX_READ;
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cmd |= max_read << 2;
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}
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if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
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cmd &= ~PCI_X_CMD_MAX_SPLIT;
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cmd |= max_tran << 4;
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}
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/* Don't attempt to handle PCI-X errors */
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cmd &= ~PCI_X_CMD_DPERR_E;
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if (orig_cmd != cmd) {
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pci_write_config16(dev, cap + PCI_X_CMD, cmd);
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}
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}
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static void amd8132_scan_bus(struct bus *bus,
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unsigned int min_devfn, unsigned int max_devfn)
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{
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struct amd8132_bus_info info;
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unsigned int pos;
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/* Find the children on the bus */
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pci_scan_bus(bus, min_devfn, max_devfn);
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/* Find the revision of the 8132 */
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info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION);
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/* Find the pcix capability and get the secondary bus status */
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pos = pci_find_capability(bus->dev, PCI_CAP_ID_PCIX);
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info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
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/* Print the PCI-X bus speed */
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printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x\n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
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/* Examine the bus and find out how loaded it is */
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info.max_func = 0;
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info.master_devices = 0;
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amd8132_walk_children(bus, amd8132_count_dev, &info);
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#if 0
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/* Disable the bus if there are no devices on it
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*/
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if (!bus->children)
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{
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unsigned int pcix_misc;
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/* Disable all of my children */
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disable_children(bus);
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/* Remember the device is disabled */
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bus->dev->enabled = 0;
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/* Disable the PCI-X clocks */
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pcix_misc = pci_read_config32(bus->dev, 0x40);
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pcix_misc &= ~(0x1f << 16);
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pci_write_config32(bus->dev, 0x40, pcix_misc);
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return;
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}
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#endif
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/* If we are in conventional PCI mode nothing more is necessary.
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*/
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if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
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return;
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}
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/* Tune the devices on the bus */
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amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info);
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}
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static void amd8132_scan_bridge(struct device *dev)
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{
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do_pci_scan_bridge(dev, amd8132_scan_bus);
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}
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static void amd8132_pcix_init(struct device *dev)
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{
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uint32_t dword;
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uint8_t byte;
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unsigned int chip_rev;
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/* Find the revision of the 8132 */
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chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
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/* Enable memory write and invalidate ??? */
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dword = pci_read_config32(dev, 0x04);
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dword |= 0x10;
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dword &= ~(1<<6); // PERSP Parity Error Response
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pci_write_config32(dev, 0x04, dword);
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if (chip_rev == 0x01) {
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/* Errata #37 */
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byte = pci_read_config8(dev, 0x0c);
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if (byte == 0x08)
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pci_write_config8(dev, 0x0c, 0x10);
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#if 0
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/* Errata #59*/
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dword = pci_read_config32(dev, 0x40);
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dword &= ~(1<<31);
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pci_write_config32(dev, 0x40, dword);
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#endif
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}
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/* Set up error reporting, enable all */
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/* system error enable */
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dword = pci_read_config32(dev, 0x04);
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dword |= (1<<8);
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pci_write_config32(dev, 0x04, dword);
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/* system and error parity enable */
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dword = pci_read_config32(dev, 0x3c);
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dword |= (3<<16);
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pci_write_config32(dev, 0x3c, dword);
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dword = pci_read_config32(dev, 0x40);
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// dword &= ~(1<<31); /* WriteChainEnable */
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dword |= (1<<31);
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dword |= (1<<7);// must set to 1
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dword |= (3<<21); //PCIErrorSerrDisable
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pci_write_config32(dev, 0x40, dword);
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/* EXTARB = 1, COMPAT = 0 */
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dword = pci_read_config32(dev, 0x48);
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dword |= (1<<3);
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dword &= ~(1<<0);
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dword |= (1<<15); //CLEARPCILOG_L
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dword |= (1<<19); //PERR FATAL Enable
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dword |= (1<<22); // SERR FATAL Enable
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dword |= (1<<23); // LPMARBENABLE
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dword |= (0x61<<24); //LPMARBCOUNT
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pci_write_config32(dev, 0x48, dword);
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dword = pci_read_config32(dev, 0x4c);
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dword |= (1<<6); //Initial prefetch for memory read line request
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dword |= (1<<9); //continuous prefetch Enable for memory read line request
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pci_write_config32(dev, 0x4c, dword);
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/* Disable Single-Bit-Error Correction [30] = 0 */
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dword = pci_read_config32(dev, 0x70);
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dword &= ~(1<<30);
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pci_write_config32(dev, 0x70, dword);
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//link
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dword = pci_read_config32(dev, 0xd4);
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dword |= (0x5c<<16);
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pci_write_config32(dev, 0xd4, dword);
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/* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
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dword = pci_read_config32(dev, 0xdc);
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dword |= (1<<1) | (1<<4); // stream disable 1 to 0, DBLINSRATE
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dword |= (1<<18)|(1<<26);
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dword &= ~((3<<16)|(3<<24));
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pci_write_config32(dev, 0xdc, dword);
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/* Set up CRC flood enable */
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dword = pci_read_config32(dev, 0xc0);
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if (dword) { /* do device A only */
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#if 0
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dword = pci_read_config32(dev, 0xc4);
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dword |= (1<<1);
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pci_write_config32(dev, 0xc4, dword);
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dword = pci_read_config32(dev, 0xc8);
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dword |= (1<<1);
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pci_write_config32(dev, 0xc8, dword);
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#endif
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if (chip_rev == 0x11) {
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/* [18] Clock Gate Enable = 1 */
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dword = pci_read_config32(dev, 0xf0);
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dword |= 0x00040008;
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pci_write_config32(dev, 0xf0, dword);
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}
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}
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return;
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}
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#define BRIDGE_40_BIT_SUPPORT 0
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#if BRIDGE_40_BIT_SUPPORT
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static void bridge_read_resources(struct device *dev)
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{
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struct resource *res;
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pci_bus_read_resources(dev);
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res = find_resource(dev, PCI_MEMORY_BASE);
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if (res) {
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res->limit = 0xffffffffffULL;
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}
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}
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static void bridge_set_resources(struct device *dev)
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{
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struct resource *res;
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res = find_resource(dev, PCI_MEMORY_BASE);
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if (res) {
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resource_t base, end;
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/* set the memory range */
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dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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res->flags |= IORESOURCE_STORED;
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base = res->base;
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end = resource_end(res);
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pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
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pci_write_config8(dev, NPUML, (base >> 32) & 0xff);
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pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
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pci_write_config8(dev, NPUMB, (end >> 32) & 0xff);
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report_resource_stored(dev, res, "");
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}
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pci_dev_set_resources(dev);
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}
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#endif /* BRIDGE_40_BIT_SUPPORT */
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static struct device_operations pcix_ops = {
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#if BRIDGE_40_BIT_SUPPORT
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.read_resources = bridge_read_resources,
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.set_resources = bridge_set_resources,
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#else
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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#endif
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.enable_resources = pci_bus_enable_resources,
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.init = amd8132_pcix_init,
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.scan_bus = amd8132_scan_bridge,
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.reset_bus = pci_bus_reset,
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};
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static const struct pci_driver pcix_driver __pci_driver = {
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.ops = &pcix_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = 0x7458,
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};
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static void ioapic_enable(struct device *dev)
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{
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uint32_t value;
|
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||||||
|
|
||||||
value = pci_read_config32(dev, 0x44);
|
|
||||||
if (dev->enabled) {
|
|
||||||
value |= ((1 << 1) | (1 << 0));
|
|
||||||
} else {
|
|
||||||
value &= ~((1 << 1) | (1 << 0));
|
|
||||||
}
|
|
||||||
pci_write_config32(dev, 0x44, value);
|
|
||||||
}
|
|
||||||
static void amd8132_ioapic_init(struct device *dev)
|
|
||||||
{
|
|
||||||
uint32_t dword;
|
|
||||||
unsigned int chip_rev;
|
|
||||||
|
|
||||||
/* Find the revision of the 8132 */
|
|
||||||
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
|
|
||||||
|
|
||||||
if (chip_rev == 0x01) {
|
|
||||||
#if 0
|
|
||||||
/* Errata #43 */
|
|
||||||
dword = pci_read_config32(dev, 0xc8);
|
|
||||||
dword |= (0x3<<23);
|
|
||||||
pci_write_config32(dev, 0xc8, dword);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
if ((chip_rev == 0x11) || (chip_rev == 0x12)) {
|
|
||||||
//for b1 b2
|
|
||||||
/* Errata #73 */
|
|
||||||
dword = pci_read_config32(dev, 0x80);
|
|
||||||
dword |= (0x1f<<5);
|
|
||||||
pci_write_config32(dev, 0x80, dword);
|
|
||||||
dword = pci_read_config32(dev, 0x88);
|
|
||||||
dword |= (0x1f<<5);
|
|
||||||
pci_write_config32(dev, 0x88, dword);
|
|
||||||
|
|
||||||
/* Errata #74 */
|
|
||||||
dword = pci_read_config32(dev, 0x7c);
|
|
||||||
dword &= ~(0x3<<30);
|
|
||||||
dword |= (0x01<<30);
|
|
||||||
pci_write_config32(dev, 0x7c, dword);
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct pci_operations pci_ops_pci_dev = {
|
|
||||||
.set_subsystem = pci_dev_set_subsystem,
|
|
||||||
};
|
|
||||||
static struct device_operations ioapic_ops = {
|
|
||||||
.read_resources = pci_dev_read_resources,
|
|
||||||
.set_resources = pci_dev_set_resources,
|
|
||||||
.enable_resources = pci_dev_enable_resources,
|
|
||||||
.init = amd8132_ioapic_init,
|
|
||||||
.scan_bus = 0,
|
|
||||||
.enable = ioapic_enable,
|
|
||||||
.ops_pci = &pci_ops_pci_dev,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct pci_driver ioapic_driver __pci_driver = {
|
|
||||||
.ops = &ioapic_ops,
|
|
||||||
.vendor = PCI_VENDOR_ID_AMD,
|
|
||||||
.device = 0x7459,
|
|
||||||
|
|
||||||
};
|
|
||||||
Loading…
Reference in New Issue