mainboard/google/kahlee: Add tis_plat_irq_status
For variants that have a cr50 tpm, this enables faster polling when interacting with the tpm. BUG=b:72838769 BRANCH=none TEST=verified on grunt that irq is used and not timeouts for tpm Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428 Signed-off-by: Chris Ching <chingcodes@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -15,8 +15,10 @@
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include <soc/southbridge.h>
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#include <soc/southbridge.h>
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#include <variant/ec.h>
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#include <variant/ec.h>
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#include <variant/gpio.h>
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void bootblock_mainboard_init(void)
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void bootblock_mainboard_init(void)
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{
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{
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@ -30,4 +32,11 @@ void bootblock_mainboard_init(void)
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/* Setup TPM decode before verstage */
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/* Setup TPM decode before verstage */
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sb_tpm_decode_spi();
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sb_tpm_decode_spi();
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/* Configure cr50 interrupt pin for use in polling tpm status */
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if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) {
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const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW |
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GPIO_INT_STATUS_EN;
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gpio_set_interrupt(H1_PCH_INT, flags);
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}
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}
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}
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@ -1,7 +1,7 @@
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#
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#
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# This file is part of the coreboot project.
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# This file is part of the coreboot project.
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#
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#
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# Copyright (C) 2017 Google, Inc.
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# Copyright (C) 2018 Google, LLC.
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#
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#
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# This program is free software; you can redistribute it and/or modify
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# it under the terms of the GNU General Public License as published by
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@ -16,7 +16,11 @@
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bootblock-y += gpio.c
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bootblock-y += gpio.c
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bootblock-y += OemCustomize.c
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bootblock-y += OemCustomize.c
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verstage-y += tpm_tis.c
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romstage-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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romstage-y += memory.c
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romstage-y += tpm_tis.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += tpm_tis.c
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@ -24,6 +24,9 @@
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# define MEM_CONFIG2 GPIO_131
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# define MEM_CONFIG2 GPIO_131
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# define MEM_CONFIG3 GPIO_132
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# define MEM_CONFIG3 GPIO_132
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/* CR50 interrupt pin */
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#define H1_PCH_INT GPIO_9
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/* SPI Write protect */
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/* SPI Write protect */
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#define CROS_WP_GPIO GPIO_122
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#define CROS_WP_GPIO GPIO_122
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#define GPIO_EC_IN_RW GPIO_15
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#define GPIO_EC_IN_RW GPIO_15
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <security/tpm/tis.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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int tis_plat_irq_status(void)
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{
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return gpio_interrupt_status(H1_PCH_INT);
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}
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@ -28,6 +28,9 @@
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#define MEM_CONFIG2 0
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#define MEM_CONFIG2 0
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#define MEM_CONFIG3 0
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#define MEM_CONFIG3 0
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/* CDX03 doesn't have a CR50 interrupt pin */
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#define H1_PCH_INT 0
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/* SPI Write protect */
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/* SPI Write protect */
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#define CROS_WP_GPIO GPIO_142
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#define CROS_WP_GPIO GPIO_142
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#define GPIO_EC_IN_RW GPIO_15
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#define GPIO_EC_IN_RW GPIO_15
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