mb/google/cherry: Add MediaTek MT8195 reference board

TEST=boot from SPI-NOR and UART works fine.

Change-Id: I279b3d2da8a30b38686005212f6c019a9a646874
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/mainboard/google/cherry/Kconfig

@@ -0,0 +1,25 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# Umbrella option to be selected by variant boards.
+config BOARD_GOOGLE_CHERRY_COMMON
+	def_bool n
+
+if BOARD_GOOGLE_CHERRY_COMMON
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_MEDIATEK_MT8195
+	select BOARD_ROMSIZE_KB_8192
+	select MAINBOARD_HAS_CHROMEOS
+	select COMMON_CBFS_SPI_WRAPPER
+	select SPI_FLASH
+	select SPI_FLASH_INCLUDE_ALL_DRIVERS
+
+config MAINBOARD_DIR
+	string
+	default "google/cherry"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Cherry" if BOARD_GOOGLE_CHERRY
+endif

src/mainboard/google/cherry/Kconfig.name

@@ -0,0 +1,5 @@
+comment "Cherry"
+
+config BOARD_GOOGLE_CHERRY
+	bool "->  Cherry"
+	select BOARD_GOOGLE_CHERRY_COMMON

src/mainboard/google/cherry/Makefile.inc

@@ -0,0 +1,13 @@
+bootblock-y += memlayout.ld
+bootblock-y += chromeos.c
+
+verstage-y += memlayout.ld
+verstage-y += chromeos.c
+verstage-y += reset.c
+
+romstage-y += memlayout.ld
+romstage-y += chromeos.c
+
+ramstage-y += memlayout.ld
+ramstage-y += chromeos.c
+ramstage-y += reset.c

src/mainboard/google/cherry/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Cherry MediaTek MT8195 reference board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/google/cherry/chromeos.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+
+}
+
+int get_recovery_mode_switch(void)
+{
+	/* TODO: use Chrome EC switches when EC support is added */
+	return 0;
+}

src/mainboard/google/cherry/chromeos.fmd

@@ -0,0 +1,45 @@
+# Firmware Layout Description for Chrome OS.
+#
+# The size and address of every section must be aligned to at least 4K, except:
+# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
+#
+# 'FMAP' may be found by binary search so its starting address should be better
+# aligned to larger values.
+#
+# For sections to be preserved on update, add (PRESERVE) to individual sections
+# instead of a group section; otherwise the preserved data may be wrong if you
+# resize or reorder sections inside a group.
+
+FLASH@0x0 8M {
+	WP_RO@0x0 4M {
+		RO_SECTION {
+			BOOTBLOCK 128K
+			FMAP 4K
+			COREBOOT(CBFS)
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_VPD(PRESERVE) 32K  # At least 16K.
+	}
+	RW_SECTION_A 1500K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 0x100
+	}
+	RW_MISC 36K {
+		RW_VPD(PRESERVE) 16K  # At least 8K.
+		RW_NVRAM(PRESERVE) 8K
+		RW_MRC_CACHE(PRESERVE) 8K
+		RW_ELOG(PRESERVE) 4K  # ELOG driver hard-coded size in 4K.
+	}
+	RW_SECTION_B 1500K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 0x100
+	}
+	RW_SHARED 36K {  # Will be force updated on recovery.
+		SHARED_DATA 4K  # 4K or less for netboot params.
+		RW_UNUSED
+	}
+	RW_LEGACY(CBFS) 1M  # Minimal 1M.
+}

src/mainboard/google/cherry/devicetree.cb

@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/mediatek/mt8195
+	device cpu_cluster 0 on
+		device cpu 0 on end
+	end
+end

src/mainboard/google/cherry/memlayout.ld

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/memlayout.ld>

src/mainboard/google/cherry/reset.c

@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <reset.h>
+
+void do_board_reset(void)
+{
+}