diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 48f65078ac..6b32c6e8e2 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -43,6 +43,7 @@ romstage-$(CONFIG_PICASSO_UART) += uart.c
 romstage-y += tsc_freq.c
 romstage-y += southbridge.c
 romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
+romstage-y += soc_util.c
 
 verstage-y += gpio.c
 verstage-y += i2c.c
@@ -74,6 +75,7 @@ ramstage-$(CONFIG_PICASSO_UART) += uart.c
 ramstage-y += usb.c
 ramstage-y += tsc_freq.c
 ramstage-y += finalize.c
+ramstage-y += soc_util.c
 
 all-y += cfg_util.c
 all-y += reset.c
diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h
new file mode 100644
index 0000000000..be05d9f9af
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/soc_util.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+int soc_is_pollock(void);
+int soc_is_dali(void);
+int soc_is_picasso(void);
+int soc_is_raven2(void);
+int soc_is_zen_plus(void);
diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c
new file mode 100644
index 0000000000..893ff2570f
--- /dev/null
+++ b/src/soc/amd/picasso/soc_util.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <arch/cpu.h>
+#include <soc/cpu.h>
+#include <soc/soc_util.h>
+
+int soc_is_pollock(void)
+{
+	return soc_is_zen_plus() && CONFIG(AMD_FT5);
+}
+
+int soc_is_dali(void)
+{
+	return soc_is_raven2() && CONFIG(AMD_FP5);
+}
+
+int soc_is_picasso(void)
+{
+	return soc_is_zen_plus() && CONFIG(AMD_FP5);
+}
+
+int soc_is_raven2(void)
+{
+	/* mask lower model number nibble and stepping */
+	return cpuid_eax(1) >> 8 == RAVEN2_CPUID >> 8;
+}
+
+int soc_is_zen_plus(void)
+{
+	/* mask lower model number nibble and stepping */
+	return cpuid_eax(1) >> 8 == PICASSO_CPUID >> 8;
+}