mb/intel/tglrvp: Update tglrvp_up3 devicetree
Update Tigerlake RVP UP3 devicetree to reflect devices used by tglrvp_up3. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Idd0d9efe0ab4e050d2160f7662e4dc40a002672f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37929 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -4,6 +4,82 @@ chip soc/intel/tigerlake
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device lapic 0 on end
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end
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# FSP configuration
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register "SaGv" = "SaGv_Disabled"
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register "SmbusEnable" = "1"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth
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register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
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register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2
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register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
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register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port3
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register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
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register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "PrmrrSize" = "0x10000000"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpEnable[9]" = "1"
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register "PcieClkSrcClkReq[1]" = "1"
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register "PcieClkSrcClkReq[2]" = "2"
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register "PcieClkSrcClkReq[3]" = "3"
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register "PcieClkSrcUsage[1]" = "0x2"
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register "PcieClkSrcUsage[2]" = "0x3"
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register "PcieClkSrcUsage[3]" = "0x8"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoGSpiCsState" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoDisabled,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoPci,
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}"
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device domain 0 on
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#From EDS(575683)
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