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soc/intel/broadwell: Clean up the bootflow 

Call the raminit from a common location instead of from the mainboard
specific code.

Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-05-12 13:47:35 +02:00 committed by Nico Huber
parent 325865db56
commit 97e9e5622d
6 changed files with 48 additions and 53 deletions
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9
src/mainboard/google/auron/romstage.c
View File

@ -27,17 +27,16 @@ __weak void variant_romstage_entry(struct romstage_params *rp)
{
}
void mainboard_romstage_entry(struct romstage_params *rp)
void mainboard_pre_raminit(struct romstage_params *rp)
{
post_code(0x32);
/* Fill out PEI DATA */
mainboard_fill_pei_data(&rp->pei_data);
mainboard_fill_spd_data(&rp->pei_data);
/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);
}
void mainboard_post_raminit(struct romstage_params *rp)
{
/* Do variant-specific init */
variant_romstage_entry(rp);
}

10
src/mainboard/google/jecht/romstage.c
View File

@ -27,17 +27,15 @@
#include "onboard.h"
void mainboard_romstage_entry(struct romstage_params *rp)
void mainboard_pre_raminit(struct romstage_params *rp)
{
post_code(0x32);
/* Fill out PEI DATA */
mainboard_fill_pei_data(&rp->pei_data);
mainboard_fill_spd_data(&rp->pei_data);
}
/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);
void mainboard_post_raminit(struct romstage_params *rp)
{
if (CONFIG(CHROMEOS))
init_bootmode_straps();
}

10
src/mainboard/intel/wtm2/romstage.c
View File

@ -22,12 +22,12 @@
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
void mainboard_romstage_entry(struct romstage_params *rp)
void mainboard_pre_raminit(struct romstage_params *rp)
{
post_code(0x32);
/* Fill out PEI DATA */
mainboard_fill_pei_data(&rp->pei_data);
romstage_common(rp);
}
void mainboard_post_raminit(struct romstage_params *rp)
{
}

9
src/mainboard/purism/librem_bdw/romstage.c
View File

@ -18,11 +18,12 @@
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
void mainboard_romstage_entry(struct romstage_params *rp)
void mainboard_pre_raminit(struct romstage_params *rp)
{
/* Fill out PEI DATA */
mainboard_fill_pei_data(&rp->pei_data);
/* Initialize memory */
romstage_common(rp);
}
void mainboard_post_raminit(struct romstage_params *rp)
{
}

4
src/soc/intel/broadwell/include/soc/romstage.h
View File

@ -27,8 +27,8 @@ struct romstage_params {
struct pei_data pei_data;
};
void mainboard_romstage_entry(struct romstage_params *params);
void romstage_common(struct romstage_params *params);
void mainboard_pre_raminit(struct romstage_params *params);
void mainboard_post_raminit(struct romstage_params *params);
void raminit(struct pei_data *pei_data);

59
src/soc/intel/broadwell/romstage/romstage.c
View File

@ -103,8 +103,34 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
/* Initialize GPIOs */
init_gpios(mainboard_gpio_config);
/* Call into mainboard. */
mainboard_romstage_entry(&rp);
/* Fill in mainboard pei_date. */
mainboard_pre_raminit(&rp);
post_code(0x32);
timestamp_add_now(TS_BEFORE_INITRAM);
rp.pei_data.boot_mode = rp.power_state->prev_sleep_state;
if (CONFIG(ELOG_BOOT_COUNT)
&& rp.power_state->prev_sleep_state != ACPI_S3)
boot_count_increment();
/* Print ME state before MRC */
intel_me_status();
/* Save ME HSIO version */
intel_me_hsio_version(&rp.power_state->hsio_version,
&rp.power_state->hsio_checksum);
/* Initialize RAM */
raminit(&rp.pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3);
mainboard_post_raminit(&rp);
platform_enter_postcar();
}
@ -117,33 +143,4 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
romstage_main(base_timestamp, bist);
}
/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
post_code(0x32);
timestamp_add_now(TS_BEFORE_INITRAM);
params->pei_data.boot_mode = params->power_state->prev_sleep_state;
#if CONFIG(ELOG_BOOT_COUNT)
if (params->power_state->prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
/* Print ME state before MRC */
intel_me_status();
/* Save ME HSIO version */
intel_me_hsio_version(&params->power_state->hsio_version,
&params->power_state->hsio_checksum);
/* Initialize RAM */
raminit(&params->pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3);
}
void __weak mainboard_pre_console_init(void) {}