soc/braswell: Fix leakage on V1P8S rail

Tristate MMC1_RCLK pin to fix leakage on V1P8S rail.

Original-Reviewed-on: https://chromium-review.googlesource.com/292043
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>

Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/12730
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

src/soc/intel/braswell/include/soc/gpio.h

@@ -105,6 +105,7 @@
 #define MMC1_D5_MMIO_OFFSET		GPIO_OFFSET(65)
 #define MMC1_D6_MMIO_OFFSET		GPIO_OFFSET(63)
 #define MMC1_D7_MMIO_OFFSET		GPIO_OFFSET(68)
+#define MMC1_RCLK_OFFSET		GPIO_OFFSET(69)
 #define HV_DDI2_DDC_SDA_MMIO_OFFSET	GPIO_OFFSET(62)
 #define HV_DDI2_DDC_SCL_MMIO_OFFSET	GPIO_OFFSET(67)
 #define CFIO_139_MMIO_OFFSET		GPIO_OFFSET(64)

src/soc/intel/braswell/smihandler.c

@@ -117,6 +117,8 @@ static void tristate_gpios(uint32_t val)
 			MMC1_D6_MMIO_OFFSET, val);
 	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
 			MMC1_D7_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
+			MMC1_RCLK_OFFSET, val);
 
 	/* Tri-state HDMI */
 	write32((void *)COMMUNITY_GPNORTH_BASE +