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nb/intel/haswell/finalize.c: Lock PCU DDR PTM 

This register has a lock bit. The Haswell System Agent BIOS Spec
revision 0.6.0 indicates it needs to be set, thus set it. Note that
Broadwell already locks this register.

Tested on Asrock B85M Pro4, still boots and register is locked.

Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46679
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-23 10:53:31 +02:00
parent 63837b0af0
commit 97f0d81503
2 changed files with 3 additions and 0 deletions
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1
src/northbridge/intel/haswell/finalize.c
View File

@ -18,6 +18,7 @@ void intel_northbridge_haswell_finalize_smm(void)
pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */
MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
MCHBAR32_OR(REQLIM, 1UL << 31);

2
src/northbridge/intel/haswell/registers/mchbar.h
View File

@ -24,6 +24,8 @@
/* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */
#define MMIO_PAVP_MSG 0x5500
#define PCU_DDR_PTM_CTL 0x5880
/* Some power MSRs are also represented in MCHBAR */
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define MCH_PKG_POWER_LIMIT_HI 0x59a4